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| 型號： | MPC604E |
| 廠商： | Motorola, Inc. |
| 英文描述： | PowerPC 604e-TM RISC Microprocessor Technical Summary |
| 中文描述： | 的PowerPC 604e -商標(biāo)RISC微處理器技術(shù)總結(jié) |
| 文件頁數(shù)： | 31/34頁 |
| 文件大?。?/td> | 117K |
| 代理商： | MPC604E |
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PowerPC 604e RISC Microprocessor Technical Summary
31
2.1.4 Instruction Timing
As shown in Figure 7, the common pipeline of the 604e has six stages through which all instructions must
pass. Some instructions occupy multiple stages simultaneously and some individual execution units have
additional stages. For example, the floating-point pipeline consists of three stages through which all
floating-point instructions must pass.
Reserved
00E10–00EFF
Not implemented on the 604e.
Performance
monitoring
interrupt
00F00
The performance monitoring interrupt is a 604e-specific exception and is used
with the 604e performance monitor, described in Section 2.3, “Performance
Monitor.”
The performance monitoring facility can be enabled to signal an exception
when the value in one of the performance monitor counter registers (PMC1–
PMC4) goes negative. The conditions that can cause this exception can be
enabled or disabled in the monitor mode control registers (MMCR0 or MMCR1).
Although the exception condition may occur when the MSR EE bit is cleared,
the actual interrupt is masked by the EE bit and cannot be taken until the EE bit
is set.
Reserved
01000–012FF
—
Instruction
address
breakpoint
01300
An instruction address breakpoint exception occurs when the address (bits 0 to
29) in the IABR matches the next instruction to complete in the completion unit,
and the IABR enable bit (bit 30) is set to 1.
System
management
interrupt
01400
A system management interrupt is caused when MSR[EE] = 1 and the SMI
input signal is asserted. This exception is provided for use with the nap mode,
which is described in Section 2.2, “Power Management—Nap Mode.”
Reserved
01500-02FFF
—
Reserved
01000–02FFF
Reserved, implementation-specific exceptions. These are not implemented in
the 604e.
Table 2. Exceptions and Conditions (Continued)
Exception
Type
Vector Offset
(hex)
Causing Conditions
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