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參數資料
| 型號： | MPC604E |
| 廠商： | Motorola, Inc. |
| 英文描述： | PowerPC 604e-TM RISC Microprocessor Technical Summary |
| 中文描述： | 的PowerPC 604e -商標RISC微處理器技術總結 |
| 文件頁數： | 32/34頁 |
| 文件大?。?/td> | 117K |
| 代理商： | MPC604E |
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PowerPC 604e RISC Microprocessor Technical Summary
Figure 7. Pipeline Diagram
The common pipeline stages are as follows:
Instruction fetch (IF)—During the IF stage, the fetch unit loads the decode queue (DEQ) with
instructions from the instruction cache and determines from what address the next instruction
should be fetched.
Instruction decode (ID)—During the ID stage, all time-critical decoding is performed on
instructions in the dispatch queue (DISQ). The remaining decode operations are performed during
the instruction dispatch stage.
Instruction dispatch (DS)—During the dispatch stage, the decoding that is not time-critical is
performed on the instructions provided by the previous ID stage. Logic associated with this stage
determines when an instruction can be dispatched to the appropriate execution unit. At the end of
the DS stage, instructions and their operands are latched into the execution input latches or into the
unit’s reservation station. Logic in this stage allocates resources such as the rename registers and
reorder buffer entries.
Execute (E)—While the execution stage is viewed as a common stage in the 604e instruction
pipeline, the instruction flow is split among the seven execution units, some of which consist of
multiple pipelines. An instruction may enter the execute stage from either the dispatch stage or the
execution unit’s dedicated reservation station.
At the end of the execute stage, the execution unit writes the results into the appropriate rename
buffer entry and notifies the completion stage that the instruction has finished execution.
Decode (ID)
Complete (C)
Writeback (W)
(Four-instruction dispatch per clock in
any combination)
SCIU1
Execute Stage
SCIU2
FPU
Fetch (IF)
Dispatch (DS)
LSU
MCIU
BPU
CPU
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