參數(shù)資料
型號(hào)： MPC740ARX233LX
廠商： FREESCALE SEMICONDUCTOR INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 233 MHz, RISC PROCESSOR, CBGA255
封裝： 21 X 21 MM, 3 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-255
文件頁(yè)數(shù)： 26/44頁(yè)
文件大?。?/td> 558K
代理商： MPC740ARX233LX
32
MPC750A RISC Microprocessor Hardware Specications
System Design Information
1.8.1 PLL Conguration
The MPC750’s PLL is congured by the PLL_CFG[0–3] signals. For a given SYSCLK (bus) frequency,
the PLL conguration signals set the internal CPU and VCO frequency of operation. The PLL
conguration for the MPC750 is shown in Table 17 for nominal frequencies.
Table 17. MPC750 Microprocessor PLL Configuration
PLL_CFG
[0–3]
Sample Bus-to-Core Frequency in MHz (VCO Frequency in MHz)
Bus-to-
Core
Multiplier
Core-to
VCO
Multiplier
Bus
25 MHz
Bus
33.3
MHz
Bus
40 MHz
Bus
50 MHz
Bus
66.6
MHz
Bus
75 MHz
Bus
83.3
MHz
1000
3x
2x
150 (300) 200
(400)
225 (450) 250
(500)
1110
3.5x
2x
175 (350) 233
(466)
262 (525)
1010
4x
2x
160 (320) 200 (400) 266
(533)
0111
4.5x
2x
150
(300)
180 (360) 225 (450)
1011
5x
2x
166
(333)
200 (400) 250 (500)
1001
5.5x
2x
183
(366)
220 (440)
1101
6x
2x
150 (300) 200
(400)
240 (480)
0101
6.5x
2x
162 (325) 216
(433)
260 (520)
0010
7x
2x
175 (350) 233
(466)
0001
7.5x
2x
187
(375)
250
(500)
1100
8x
2x
200
(400)
266
(533)
0011
PLL off/bypass
PLL off, SYSCLK clocks core circuitry directly, 1x bus-to-core implied
1111
PLL off
PLL off, no core clocking occurs
Notes:
1. PLL_CFG[0–3] settings not listed are reserved.
2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core, or VCO
frequencies which are not useful, not supported, or not tested for by the MPC750; see Section 1.4.2.1, “Clock AC
Specifications,” for valid SYSCLK and VCO frequencies.
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode is
set for 1:1 mode operation. This mode is intended for factory use only.
Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.
4. In clock-off mode, no clocking occurs inside the MPC750 regardless of the SYSCLK input.
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For More Information On This Product,
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