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參數(shù)資料
| 型號： | MPC8241LZP200X |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA357 |
| 封裝： | 25 X 25 MM, PLASTIC, BGA-357 |
| 文件頁數(shù)： | 54/56頁 |
| 文件大?。?/td> | 739K |
| 代理商： | MPC8241LZP200X |
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MOTOROLA
MPC8241 Integrated Processor Hardware Specifications
7
Electrical and Thermal Characteristics
1.4.1.2
Recommended Operating Conditions
Table 2 provides the recommended operating conditions for the MPC8241.
Table 2. Recommended Operating Conditions
Characteristic
Symbol
Recommended
Value
Unit
Notes
Supply voltage
VDD
1.8
±100 mV
V
1, 2
I/O buffer supply for PCI and standard;
supply voltages for memory bus drivers
GVDD_OVDD
3.3
±10%
V
2
CPU PLL supply voltage
AVDD
1.8
±100 mV
1, 2
PLL supply voltage—peripheral logic
AVDD21.8 ±100 mV
V
1, 3
PCI reference
LVDD
5.0
±5%
V
4, 5, 6
3.3
±0.3
V
5, 6, 7
Input voltage
PCI inputs
Vin
0 to 3.6 or 5.75
V
2, 3
All other inputs
0 to 3.6
V
8
Die-junction temperature
Tj
0 to 105
°C
Notes:
1. CPU speed limited to 200 MHz operation at this voltage. See Table 7.
2. Caution: GVDD_OVDD must not exceed VDD/AVDD/AVDD2 by more than 1.8 V at any time including during
power-on reset. Note that GVDD_OVDD pins are all shorted together: PWRRING. Connections should not be
made to individual PWRRING pins.
3. Caution: VDD/AVDD/AVDD2 must not exceed GVDD_OVDD by more than 0.6 V at any time, including during
power-on reset.
4. PCI pins are designed to withstand LVDD + 0.5 V DC when LVDD is connected to a 5.0 V DC power supply.
5. Caution: LVDD must not exceed VDD/AVDD/AVDD2 by more than 5.4 V at any time, including during power-on
reset.
6. Caution: LVDD must not exceed GVDD_OVDD by more than 3.0 V at any time, including during power-on reset.
7. PCI pins are designed to withstand LVDD + 0.5 V DC when LVDD is connected to a 3.3 V DC power supply.
8. Caution: Input voltage (Vin) must not be greater than the supply voltage (VDD/AVDD/AVDD2) by more than 2.5 V at
all times including during power-on reset. Input voltage (Vin) must not be greater than GVDD_OVDD by more than
0.6 V at all times including during power-on reset.
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