參數(shù)資料
型號(hào): MPC8245LZU333B
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 333 MHz, RISC PROCESSOR, PBGA352
封裝: 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, CAVITY-UP, TBGA-352
文件頁(yè)數(shù): 24/64頁(yè)
文件大?。?/td> 940K
代理商: MPC8245LZU333B
30
MPC8245 Integrated Processor Hardware Specifications
MOTOROLA
Electrical and Thermal Characteristics
Figure 21. PIC Serial Interrupt Mode Input Timing Diagram
1.4.3.6
IEEE 1149.1 (JTAG) AC Timing Specifications
Table 16 provides the JTAG AC timing specifications for the MPC8245 while in the JTAG operating mode
at recommended operating conditions (see Table 2) with LVDD = 3.3 V ± 0.3 V. Timings are independent of
the system clock (PCI_SYNC_IN).
Figure 22. JTAG Clock Input Timing Diagram
Table 16. JTAG AC Timing Specification (Independent of PCI_SYNC_IN)
Num
Characteristic
Min
Max
Unit
Notes
TCK frequency of operation
0
25
MHz
1
TCK cycle time
40
ns
2
TCK clock pulse width measured at 1.5 V
20
ns
3
TCK rise and fall times
0
3
ns
4TRST setup time to TCK falling edge
10
ns
1
5TRST assert time
10
ns
6
Input data setup time
5
ns
2
7
Input data hold time
15
ns
2
8
TCK to output data valid
0
30
ns
3
9
TCK to output high impedance
0
30
ns
3
10
TMS, TDI Data setup time
5
ns
11
TMS, TDI data hold time
15
ns
12
TCK to TDO data valid
0
15
ns
13
TCK to TDO high impedance
0
15
ns
Notes:
1. TRST is an asynchronous signal. The setup time is for test purposes only.
2. Nontest (other than TDI and TMS) signal input timing with respect to TCK.
3. Nontest (other than TDO) signal output timing with respect to TCK.
6
S_CLK
S_INT
7
VM
TCK
2
1
VM
3
VM = Midpoint Voltage
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