參數(shù)資料
型號(hào)： MPC8245TZU333D
廠商： MOTOROLA INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 333 MHz, RISC PROCESSOR, PBGA352
封裝： 35 X 35 MM, 1.70 MM HEIGHT, 1.27 MM PITCH, CAVITY-UP, TBGA-352
文件頁(yè)數(shù)： 11/60頁(yè)
文件大?。?/td> 674K
代理商： MPC8245TZU333D
MOTOROLA
MPC8245 Integrated Processor Hardware Specications
19
Electrical and Thermal Characteristics
Table 10. Input AC Timing Specications
Num
Characteristic
Min
Max
Unit
Notes
10a
PCI input signals valid to PCI_SYNC_IN (input setup)
3.0
—
ns
1, 3
10b
Memory input signals valid to SDRAM_SYNC_IN (input setup)
10b0
Tap 0, register offset <0x77>, bits 5:4 = 0b00
2.6
—
ns
2, 3, 6
10b1
Tap 1, register offset <0x77>, bits 5:4 = 0b01
1.9
—
10b2
Tap 2, register offset <0x77>, bits 5:4 = 0b10 (default)
1.2
—
10b3
Tap 3, register offset <0x77>, bits 5:4 = 0b11
0.5
—
10c
PIC, misc. debug input signals valid to SDRAM_SYNC_IN
(input setup)
3.0
—
ns
2, 3
10d
I2C input signals valid to SDRAM_SYNC_IN (input setup)
3.0
—
ns
2, 3
10e
Mode select inputs valid to HRST_CPU/HRST_CTRL (input
setup)
9
× tCLK
—
ns
2, 3–5
11
Tos—SDRAM_SYNC_IN to sys_logic_clk offset time
0.65
1.0
ns
7
11a
SDRAM_SYNC_IN to memory signal inputs invalid (input hold)
11a0
Tap 0, register offset <0x77>, bits 5:4 = 0b00
0
—
ns
2, 3, 6
11a1
Tap 1, register offset <0x77>, bits 5:4 = 0b01
0.7
—
11a2
Tap 2, register offset <0x77>, bits 5:4 = 0b10 (default)
1.4
—
11a3
Tap 3, register offset <0x77>, bits 5:4 = 0b11
2.1
—
11b
HRST_CPU/HRST_CTRL to mode select inputs invalid (input
hold)
0
—
ns
2, 3, 5
11c
PCI_SYNC_IN to Inputs invalid (input hold)
1.0
—
ns
1, 2, 3
Notes:
1. All PCI signals are measured from OVDD/2 of the rising edge of PCI_SYNC_IN to 0.4 × OVDD of the signal in
question for 3.3 V PCI signaling levels. See Figure 10.
2. All memory and related interface input signal specications are measured from the TTL level (0.8 or 2.0 V) of the
signal in question to the VM = 1.4 V of the rising edge of the memory bus clock, SDRAM_SYNC_IN.
SDRAM_SYNC_IN is the same as PCI_SYNC_IN in 1:1 mode, but is twice the frequency in 2:1 mode
(processor/memory bus clock rising edges occur on every rising and falling edge of PCI_SYNC_IN). See Figure 9.
3. Input timings are measured at the pin.
4. tCLK is the time of one SDRAM_SYNC_IN clock cycle.
5. All mode select input signals specications are measured from the TTL level (0.8 or 2.0 V) of the signal in question
to the VM = 1.4 V of the rising edge of the HRST_CPU/HRST_CTRL signal. See Figure 11.
6. The memory interface input setup and hold times are programmable to four possible combinations by programming
bits 5:4 of register offset <0x77> to select the desired input setup and hold times.
7. Tos represents a timing adjustment for SDRAM_SYNC_IN with respect to sys_logic_clk. Due to the internal delay
present on the SDRAM_SYNC_IN signal with respect to the sys_logic_clk inputs to the DLL, the resulting SDRAM
clocks become offset by the delay amount. The feedback trace length of SDRAM_SYNC_OUT to
SDRAM_SYNC_IN must be shortened by this amount relative to the SDRAM clock output trace lengths to maintain
phase-alignment of the memory clocks with respect to sys_logic_clk. Note that the DLL locking range graphs of
Figure 5 through Figure 8 compensate for Tos and there is no additional requirement to shorten Tloop by the duration
of Tos. Refer to Motorola Application Note AN2164, MPC8245/MPC8241 Memory Clock Design Guidelines, for
more details on accommodating for the problem of Tos and trace measurements in general.
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