參數(shù)資料
型號(hào)： MPC8247ZQTMFA
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 25/61頁(yè)
文件大?。?/td> 0K
描述： IC MPU POWERQUICC II 516-PBGA
標(biāo)準(zhǔn)包裝： 40
系列： MPC82xx
處理器類型： 32-位 MPC82xx PowerQUICC II
速度： 400MHz
電壓： 1.5V
安裝類型： 表面貼裝
封裝/外殼： 516-BBGA
供應(yīng)商設(shè)備封裝： 516-FPBGA（27x27）
包裝： 托盤
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
Freescale Semiconductor
31
Clock Configuration Modes
1011_100
80.0
106.7
2.5
200.0 266.6
4
320.0 426.6
4
50.0
66.7
1011_101
80.0
106.7
2.5
200.0 266.6
4.5
360.0 480.0
4
50.0
66.7
1101_000
100.0 133.3
2.5
250.0 333.3
3
300.0 400.0
5
50.0
66.7
1101_001
100.0 133.3
2.5
250.0 333.3
3.5
350.0 466.6
5
50.0
66.7
1101_010
100.0 133.3
2.5
250.0 333.3
4
400.0 533.3
5
50.0
66.7
1101_011
100.0 133.3
2.5
250.0 333.3
4.5
450.0 599.9
5
50.0
66.7
1101_100
100.0 133.3
2.5
250.0 333.3
5
500.0 666.6
5
50.0
66.7
1101_101
125.0 166.7
2
250.0 333.3
3
375.0 500.0
5
50.0
66.7
1101_110
125.0 166.7
2
250.0 333.3
4
500.0 666.6
5
50.0
66.7
1110_000
100.0 133.3
3
300.0 400.0
3.5
350.0 466.6
6
50.0
66.7
1110_001
100.0 133.3
3
300.0 400.0
4
400.0 533.3
6
50.0
66.7
1110_010
100.0 133.3
3
300.0 400.0
4.5
450.0 599.9
6
50.0
66.7
1110_011
100.0 133.3
3
300.0 400.0
5
500.0 666.6
6
50.0
66.7
1110_100
100.0 133.3
3
300.0 400.0
5.5
550.0 733.3
6
50.0
66.7
1100_000
Reserved
1100_001
Reserved
1100_010
Reserved
1 The “l(fā)ow” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency in a
table entry guarantees only the required minimum CPU operating frequency. The “high” values are for the purpose of
illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed
the frequency rating of the user’s device. The minimum CPU frequency is 150 MHz for commercial temperature
devices and 175 MHz for extended temperature devices. The minimum CPM frequency is 120 MHz.
2 PCI_MODCK determines the PCI clock frequency range. SeeTable 18 for lower range configurations.
3 MODCK_H = hard reset configuration word [28–31] (see Section 5.4 in the SoC reference manual). MODCK[1-3] =
three hardware configuration pins.
4 CPM multiplication factor = CPM clock/bus clock
5 CPU multiplication factor = Core PLL multiplication factor
6 CPM_CLK/PCI_CLK ratio. When PCI_MODCK = 0, the ratio of CPM_CLK/PCI_CLK should be calculated from
SCCR[PCIDF] as follows:
CPM_CLK/PCI_CLK = (PCIDF + 1) / 2.
Table 17. Clock Configurations for PCI Host Mode (PCI_MODCK=0)1,2 (continued)
Mode3
Bus Clock
(MHz)
CPM
Multiplication
Factor4
CPM Clock
(MHz)
CPU
Multiplication
Factor5
CPU Clock
(MHz)
PCI
Division
Factor6
PCI Clock
(MHz)
MODCK_H-
MODCK[1-3]
Low
High
Low
High
Low
High
Low
High
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