參數(shù)資料
型號： MPC8271CZQMIBA
廠商： Freescale Semiconductor
文件頁數(shù)： 55/61頁
文件大?。?/td> 0K
描述： IC MPU POWERQUICC II 516-PBGA
標準包裝： 40
系列： MPC82xx
處理器類型： 32-位 MPC82xx PowerQUICC II
速度： 266MHz
電壓： 1.5V
安裝類型： 表面貼裝
封裝/外殼： 516-BBGA
供應(yīng)商設(shè)備封裝： 516-FPBGA（27x27）
包裝： 托盤
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
Freescale Semiconductor
59
Document Revision History
1.2
09/2005
Added 133-MHz to the list of frequencies in the opening sentence of Section 6, “AC Electrical
Added 133 MHz columns to Table 9, Table 11, Table 12, and Table 13.
Added footnote 2 to Table 13.
Added the conditions note directly above Table 12.
1.1
01/2005
Modification for correct display of assertion level (“overbar”) for some signals
1.0
12/2004
Section 1.1: Added 8:1 ratio to Internal CPM/bus clock multiplier values
Section 2: removed voltage tracking note
Table 3: Note 2 updated regarding VDD/VCCSYN relationship to VDDH during power-on reset
Table 4: Updated VDD and VCCSYN to 1.425 V - 1.575 V
Table 8: Note 2 updated to reflect VIH=2.5 for TCK, TRST, PORESET; request for external
pull-up removed.
Section 4.6: Updated description of layout practices
Table 8: Note 3 added regarding IIC compatibility
Table 8: Updated nominal and maximum power dissipation values
Table 9: updated PCI impedance to 27
Ω, updated 60x and MEMC values and added note to
reflect configurable impedance
Section 6: Added sentence providing derating factor
Section 6.1: added Note: Rise/Fall Time on CPM Input Pins
Table 9: updated values for following specs: sp36b, sp37a, sp38a, sp39a, sp38b, sp40, sp41,
sp42, sp43, sp42a
Table 11: updated values for following specs: sp16a, sp16b, sp18a, sp18b, sp20, sp21, sp22
Section 6.2: added spread spectrum clocking note
Section 6.2: added CLKIN jitter note
Table 12: combined specs sp11 and sp11a
Table 13: sp30 Data Bus minimum delay values changed to 0.8
Section 7: unit of ns added to Tval notes
Section 7: Updated all notes to reflect updated CPU Fmin of 150 MHz commercial temp
devices, 175 MHz extended temp; CPM Fmin of 120 MHz.
Section 7, “Clock Configuration Modes”: Updated all table footnotes reflect updated CPU Fmin
of 150 MHz commercial temp devices, 175 MHz extended temp; CPM Fmin of 120 MHz.
Table 21: correct superscript of footnote number after pin AD22
Table 21: remove DONE3 from PC12
Table 21: signals referring to TDMs C2 and D2 removed
Table 23. Document Revision History (continued)
Revision
Date
Substantive Changes
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