參數(shù)資料
型號: MPC8306CVMADDCA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 266 MHz, RISC PROCESSOR, PBGA369
封裝: 19 X 19 MM, 1.61 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, MAPBGA-369
文件頁數(shù): 26/76頁
文件大?。?/td> 474K
代理商: MPC8306CVMADDCA
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
32
Freescale Semiconductor
HDLC
Figure 21 represents the AC timing from Table 29. Note that although the specifications generally
reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the
active edge.
Figure 21. TDM/SI AC Timing (External Clock) Diagram
10 HDLC
This section describes the DC and AC electrical specifications for the high level data link control (HDLC),
of the MPC8306.
10.1
HDLC DC Electrical Characteristics
Table 30 provides the DC electrical characteristics for the MPC8306 HDLC protocol.
10.2
HDLC AC Timing Specifications
Table 31 provides the input and output AC timing specifications for HDLC protocol.
Table 30. HDLC DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Output high voltage
VOH
IOH = –2.0 mA
2.4
V
Output low voltage
VOL
IOL = 3.2 mA
0.5
V
Input high voltage
VIH
—2.0
OVDD +0.3
V
Input low voltage
VIL
—–0.3
0.8
V
Input current
IIN
0 V
VIN OVDD
±5
A
Table 31. HDLC AC Timing Specifications1
Characteristic
Symbol2
Min
Max
Unit
Outputs—Internal clock delay
tHIKHOV
09
ns
Outputs—External clock delay
tHEKHOV
1
12
ns
Outputs—Internal clock high impedance
tHIKHOX
05.5
ns
TDM/SICLK (Input)
tSEIXKH
tSEIVKH
tSEKHOV
Input Signals:
TDM/SI
(See Note)
Output Signals:
TDM/SI
(See Note)
Note:
The clock edge is selectable on TDM/SI.
tSEKHOX
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