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參數(shù)資料
| 型號： | MPC8306CVMADDCA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 266 MHz, RISC PROCESSOR, PBGA369 |
| 封裝： | 19 X 19 MM, 1.61 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, MAPBGA-369 |
| 文件頁數(shù)： | 5/76頁 |
| 文件大?。?/td> | 474K |
| 代理商： | MPC8306CVMADDCA |
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MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
Freescale Semiconductor
13
RESET Initialization
5
RESET Initialization
This section describes the AC electrical specifications for the reset initialization timing requirements of
the MPC8306. Table 9 provides the reset initialization AC timing specifications for the reset
component(s).
Table 10 provides the PLL lock times.
5.1
Reset Signals DC Electrical Characteristics
Table 11 provides the DC electrical characteristics for the MPC8306 reset signals mentioned in Table 9.
SYS_CLK_IN duty cycle
tKHK/tSYS_CLK_
IN
40
—
60
%
3
SYS_CLK_IN jitter
—
±150
ps
4, 5
Notes:
1. Caution: The system, core and QUICC Engine block must not exceed their respective maximum or minimum operating
frequencies.
2. Rise and fall times for SYS_CLK_IN are measured at 0.33 and 2.97 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. The SYS_CLK_IN driver’s closed loop jitter bandwidth should be < 500 kHz at –20 dB. The bandwidth must be set low to
allow cascade-connected PLL-based devices to track SYS_CLK_IN drivers with the specified jitter.
6. Spread spectrum is allowed upto 1% down-spread @ 33kHz (max rate).
Table 9. RESET Initialization Timing Specifications
Parameter/Condition
Min
Max
Unit
Notes
Required assertion time of HRESET to activate reset flow
32
—
tSYS_CLK_IN
1
Required assertion time of PORESET with stable clock applied to
SYS_CLK_IN
32
—
tSYS_CLK_IN
1
HRESET assertion (output)
512
—
tSYS_CLK_IN
1
Input setup time for POR configuration signals
(CFG_RESET_SOURCE[0:3]) with respect to negation of PORESET
4—
tSYS_CLK_IN
1, 2
Input hold time for POR config signals with respect to negation of
HRESET
0
—
ns
1, 2
Notes:
1. tSYS_CLK_IN is the clock period of the input clock applied to SYS_CLK_IN. For more details, see the MPC8306
PowerQUICC II Pro Integrated Communications Processor Reference Manual
.
2. POR configuration signals consists of CFG_RESET_SOURCE[0:3].
Table 10. PLL Lock Times
Parameter/Condition
Min
Max
Unit
Notes
PLL lock times
—
100
s—
Table 8. SYS_CLK_IN AC Timing Specifications
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|---|---|
| MPC8306CVMAFDCA | 功能描述:微處理器 - MPU E300 MP ext tmp 333 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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| MPC8306-KIT | 制造商:Freescale Semiconductor 功能描述:MPC830x Processor Evaluation Kit |
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