參數(shù)資料
型號: MPC8306SCVMADDCA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 266 MHz, RISC PROCESSOR, PBGA369
封裝: 19 X 19 MM, 1.61 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, MAPBGA-369
文件頁數(shù): 54/71頁
文件大?。?/td> 452K
代理商: MPC8306SCVMADDCA
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
58
Freescale Semiconductor
Clocking
20.2
System PLL Configuration
The system PLL is controlled by the RCWL[SPMF] parameter. Table 49 shows the multiplication factor
encodings for the system PLL.
NOTE
System PLL VCO frequency = 2 × (CSB frequency) × (System PLL VCO
divider). The VCO divider needs to be set properly so that the System PLL
VCO frequency is in the range of 450–750 MHz.
As described in Section 20, “Clocking,” the LBCM, DDRCM, and SPMF parameters in the reset
configuration word low select the ratio between the primary clock input (SYS_CLK_IN) and the internal
coherent system bus clock (csb_clk). Table 50 shows the expected frequency values for the CSB frequency
for selected csb_clk to SYS_CLK_IN ratios.
Table 49. System PLL Multiplication Factors
RCWL[SPMF]
System PLL Multiplication Factor
0000
Reserved
0001
Reserved
0010
× 2
0011
× 3
0100
× 4
0101
× 5
0110
× 6
0111–1111
Reserved
Table 50. CSB Frequency Options
SPMF
csb_clk : sys_clk_in Ratio
SYS_CLK_IN(MHz)
25
33.33
66.67
csb_clk Frequency (MHz)
0010
2:1
133
0011
3:1
0100
4:1
133
0101
5:1
125
0110
6:1
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