參數(shù)資料
型號(hào): MPC8306SCVMADDCA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 266 MHz, RISC PROCESSOR, PBGA369
封裝: 19 X 19 MM, 1.61 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, MAPBGA-369
文件頁數(shù): 57/71頁
文件大?。?/td> 452K
代理商: MPC8306SCVMADDCA
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
60
Freescale Semiconductor
Clocking
20.4
QUICC Engine PLL Configuration
The QUICC Engine PLL is controlled by the RCWL[CEPMF] and RCWL[CEPDF] parameters. Table 52
shows the multiplication factor encodings for the QUICC Engine PLL.
The RCWL[CEVCOD] denotes the QUICC Engine PLL VCO internal frequency as shown in Table 53.
NOTE
The VCO divider (RCWL[CEVCOD]) must be set properly so that the
QUICC Engine VCO frequency is in the range of 300–600 MHz. The
QUICC Engine frequency is not restricted by the CSB and core frequencies.
The CSB, core, and QUICC Engine frequencies should be selected
according to the performance requirements.
The QUICC Engine VCO frequency is derived from the following
equations:
qe_clk = (primary clock input × CEPMF)
(1 + CEPDF)
QUICC Engine VCO Frequency = qe_clk × VCO divider × (1 + CEPDF)
Table 52. QUICC Engine PLL Multiplication Factors
RCWL[CEPMF]
RCWL[CEPDF]
QUICC Engine PLL Multiplication Factor = RCWL[CEPMF]/
(1 + RCWL[CEPDF)
00000–00001
0
Reserved
00010
0
2
00011
0
3
00100
0
4
00101
0
5
00110
0
6
00111
0
7
01000
0
8
01001–11111
0
Reserved
Table 53. QUICC Engine PLL VCO Divider
RCWL[CEVCOD]
VCO Divider
00
2
01
4
10
8
11
Reserved
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