This table provides the input AC timi" />
參數(shù)資料
型號(hào): MPC8313CZQAFFB
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 9/99頁(yè)
文件大?。?/td> 0K
描述: IC MPU POWERQUICC II PRO 516PBGA
標(biāo)準(zhǔn)包裝: 40
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 333MHz
電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
封裝/外殼: 516-BBGA 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 516-PBGAPGE(27x27)
包裝: 托盤(pán)
配用: MPC8313E-RDB-ND - BOARD PROCESSOR
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
17
This table provides the input AC timing specifications for the DDR SDRAM when GVDD(typ) = 2.5 V.
This table provides the input AC timing specifications for the DDR2 SDRAM interface.
This figure illustrates the DDR input timing diagram showing the tDISKEW timing parameter.
Figure 4. DDR Input Timing Diagram
Table 18. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface
At recommended operating conditions with GVDD of 2.5 ± 5%.
Parameter
Symbol
Min
Max
Unit
Note
AC input low voltage
VIL
—MVREF – 0.31
V
AC input high voltage
VIH
MVREF + 0.31
V
Table 19. DDR and DDR2 SDRAM Input AC Timing Specifications
At recommended operating conditions. with GVDD of 2.5 ± 5%.
Parameter
Symbol
Min
Max
Unit
Note
Controller skew for MDQS—MDQ
tCISKEW
ps
1, 2
333 MHz
–750
750
266 MHz
–750
750
Notes:
1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that
is captured with MDQS[n]. This should be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW. This can be
determined by the following equation: tDISKEW = ± (T/4 – abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the
absolute value of tCISKEW.
MCK[n]
tMCK
MDQ[x]
MDQS[n]
D1
D0
tDISKEW
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