參數(shù)資料
型號: MPC8313ECVRAFFB
廠商: Freescale Semiconductor
文件頁數(shù): 35/99頁
文件大?。?/td> 0K
描述: IC MPU POWERQUICC II PRO 516PBGA
標(biāo)準(zhǔn)包裝: 40
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 333MHz
電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
封裝/外殼: 516-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 516-PBGAPGE(27x27)
包裝: 托盤
配用: MPC8313E-RDB-ND - BOARD PROCESSOR
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
40
Freescale Semiconductor
Figure 25. Differential Reference Clock Input DC Requirements (External AC-Coupled)
Figure 26. Single-Ended Reference Clock Input DC Requirements
9.2.3
Interfacing With Other Differential Signaling Levels
With on-chip termination to XCOREVSS, the differential reference clocks inputs are HCSL
(high-speed current steering logic) compatible DC coupled.
Many other low voltage differential type outputs like LVDS (low voltage differential signaling) can
be used but may need to be AC coupled due to the limited common mode input range allowed (100
to 400 mV) for DC-coupled connection.
LVPECL outputs can produce a signal with too large of an amplitude and may need to be
DC-biased at the clock driver output first, then followed with series attenuation resistor to reduce
the amplitude, in addition to AC coupling.
NOTE
Figure 27 through Figure 30 are for conceptual reference only. Due to the
fact that the clock driver chip's internal structure, output impedance, and
termination requirements are different between various clock driver chip
manufacturers, it is possible that the clock circuit reference designs
provided by clock driver chip vendors are different from what is shown in
the figures. They might also vary from one vendor to the other. Therefore,
Freescale can neither provide the optimal clock driver reference circuits, nor
guarantee the correctness of the following clock driver connection reference
circuits. It is recommended that the system designer contact the selected
clock driver chip vendor for the optimal reference circuits for the
MPC8313E SerDes reference clock receiver requirement provided in this
document.
SD_REF_CLK
Vcm
200 mV < Input Amplitude or Differential Peak < 800 mV
Vmax < Vcm + 400 mV
Vmin > Vcm – 400 mV
SD_REF_CLK
400 mV < SD_REF_CLK Input Amplitude < 800 mV
0V
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