This figure provides the AC test load" />
參數(shù)資料
型號(hào)： MPC8313ECVRAFFB
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 51/99頁(yè)
文件大小： 0K
描述： IC MPU POWERQUICC II PRO 516PBGA
標(biāo)準(zhǔn)包裝： 40
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 333MHz
電壓： 0.95 V ~ 1.05 V
安裝類型： 表面貼裝
封裝/外殼： 516-BBGA 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 516-PBGAPGE（27x27）
包裝： 托盤(pán)
配用： MPC8313E-RDB-ND - BOARD PROCESSOR
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
55
This figure provides the AC test load for the I2C.
Figure 46. I2C AC Test Load
Data hold time:
CBUS compatible masters
I2C bus devices
tI2DXKL
—
02
—
0.93
s
Fall time of both SDA and SCL signals5
tI2CF
—300
ns
Setup time for STOP condition
tI2PVKH
0.6
—
s
Bus free time between a STOP and START condition
tI2KHDX
1.3
—
s
Noise margin at the LOW level for each connected device (including
hysteresis)
VNL
0.1
NV
DD
—V
Noise margin at the HIGH level for each connected device (including
hysteresis)
VNH
0.2
NV
DD
—V
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I
2C timing
(I2) with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to
the high (H) state or setup time. Also, tI2SXKL symbolizes I
2C timing (I2) for the time that the data with respect to the start
condition (S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH
symbolizes I2C timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative
to the tI2C clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used
with the appropriate letter: R (rise) or F (fall).
2. The MPC8313E provides a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge
the undefined region of the falling edge of SCL.
3. The maximum tI2DVKH has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal.
4. CB = capacitance of one bus line in pF.
5. The MPC8313E does not follow the I2C-BUS Specifications, Version 2.1, regarding the tI2CF AC parameter.
Table 49. I2C AC Electrical Specifications (continued)
All values refer to VIH (min) and VIL (max) levels (see Table 48).
Parameter
Symbol1
Min
Max
Unit
Output
Z0 = 50
NVDD/2
RL = 50
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