參數(shù)資料
型號: MPC8313ECVRAFFB
廠商: Freescale Semiconductor
文件頁數(shù): 79/99頁
文件大小: 0K
描述: IC MPU POWERQUICC II PRO 516PBGA
標準包裝: 40
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 333MHz
電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
封裝/外殼: 516-BBGA 裸露焊盤
供應商設備封裝: 516-PBGAPGE(27x27)
包裝: 托盤
配用: MPC8313E-RDB-ND - BOARD PROCESSOR
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
80
Freescale Semiconductor
As described in Section 20, “Clocking,” the LBCM, DDRCM, and SPMF parameters in the reset
configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the
primary clock input (SYS_CLK_IN or PCI_SYNC_IN) and the internal coherent system bus clock
(csb_clk). This table shows the expected frequency values for the CSB frequency for select csb_clk to
SYS_CLK_IN/PCI_SYNC_IN ratios.
0100
4
0101
5
0110
6
0111–1111
Reserved
Note:
1. If RCWL[DDRCM] and RCWL[LBCM] are both cleared, the system
PLL VCO frequency = (CSB frequency) × (System PLL VCO Divider).
2. If either RCWL[DDRCM] or RCWL[LBCM] are set, the system PLL
VCO frequency = 2 × (CSB frequency) × (System PLL VCO Divider).
3. The VCO divider needs to be set properly so that the System PLL
VCO frequency is in the range of 450–750 MHz
Table 66. CSB Frequency Options
CFG_CLKIN_DIV
at Reset1
1 CFG_CLKIN_DIV select the ratio between SYS_CLK_IN and PCI_SYNC_OUT.
SPMF
csb_clk :Input
Clock Ratio2
2 SYS_CLK_IN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
Input Clock Frequency (MHz)2
24
25
33.33
66.67
csb_clk Frequency (MHz)
High
0010
2:1
133
High
0011
3:1
100
High
0100
4:1
100
133
High
0101
5:1
120
125
167
High
0110
6:1
144
150
Low
0010
2:1
133
Low
0011
3:1
100
Low
0100
4:11
100
133
Low
0101
5:1
120
125
167
Low
0110
6:1
144
150
Table 65. System PLL Multiplication Factors (continued)
RCWL[SPMF]
System PLL
Multiplication Factor
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