參數(shù)資料
型號(hào): MPC8313ECVRAGDB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, MICROPROCESSOR, PBGA516
封裝: 27 X 27 MM, 2.25 MM HEIGHT, 1 MM PITCH, LEAD FREE, TEPBGAII-516
文件頁(yè)數(shù): 88/100頁(yè)
文件大?。?/td> 1247K
代理商: MPC8313ECVRAGDB
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 3
88
Freescale Semiconductor
System Design Information
22 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8313E SYS_CLK_IN
22.1
System Clocking
The MPC8313E includes three PLLs.
1. The platform PLL (AVDD2) generates the platform clock from the externally supplied
SYS_CLK_IN input in PCI host mode or SYS_CLK_IN/PCI_SYNC_IN in PCI agent mode. The
frequency ratio between the platform and SYS_CLK_IN is selected using the platform PLL ratio
configuration bits as described in Section 20.1, “System PLL Configuration.”
2. The e300 core PLL (AVDD1) generates the core clock as a slave to the platform clock. The
frequency ratio between the e300 core clock and the platform clock is selected using the e300
PLL ratio configuration bits as described in Section 20.2, “Core PLL Configuration.
3. There is a PLL for the SerDes block.
22.2
PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins (AVDD1,
AVDD2, and SDAVDD, respectively). The AVDD level should always be equivalent to VDD, and preferably
these voltages are derived directly from VDD through a low frequency filter scheme such as the following.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide independent filter circuits as illustrated in Figure 58, one to each of the five AVDD pins. By
providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the
other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum effective series inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AVDD
pin, which is on the periphery of package, without the inductance of vias.
Figure 58 shows the PLL power supply filter circuits.
Figure 58. PLL Power Supply Filter Circuit
VDD
AVDD1 and AVDD2
Low ESL Surface Mount Capacitors
1.0
Ω
2.2 F
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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