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| 型號(hào)： | MPC8314EVRAGDA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROPROCESSOR, PBGA620 |
| 封裝： | 29 X 29 MM, LEAD FREE, PLASTIC, TEPBGA-620 |
| 文件頁數(shù)： | 28/106頁 |
| 文件大小： | 1253K |
| 代理商： | MPC8314EVRAGDA |
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MPC8314E PowerQUICC II Pro Processor Hardware Specifications, Rev. 0
28
Freescale Semiconductor
Ethernet: Three-Speed Ethernet, MII Management
Figure 14 shows the RMII receive AC timing diagram.
Figure 14. RMII Receive AC Timing Diagram
9.2.3
RGMII and RTBI AC Timing Specifications
Table 29 presents the RGMII and RTBI AC timing specifications.
Table 29. RGMII and RTBI AC Timing Specifications
At recommended operating conditions (see Table 2)
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
Data to clock output skew (at transmitter)
tSKRGT
–0.6
—
0.6
ns
Data to clock input skew (at receiver) 2
tSKRGT
1.0
—
2.6
ns
Clock cycle duration 3
tRGT
7.2
8.0
8.8
ns
Duty cycle for 1000Base-T 4, 5
tRGTH/tRGT
45
50
55
%
Duty cycle for 10BASE-T and 100BASE-TX 3, 5
tRGTH/tRGT
40
50
60
%
Rise time (20%–80%)
tRGTR
—
0.75
ns
Fall time (20%–80%)
tRGTF
—
0.75
ns
GTX_CLK125 reference clock period
tG12
6
—8.0
—
ns
GTX_CLK125 reference clock duty cycle
tG125H/tG125
47
—
53
%
Notes:
1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent
RGMII and RTBI timing. For example, the subscript of tRGT represents the RTBI (T) receive (RX) clock. Note also that the
notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews,
the subscript is skew (SK) followed by the clock that is being skewed (RGT).
2. This implies that PC board design requires clocks to be routed so that an additional trace delay of greater than 1.5 ns is added
to the associated clock signal.
3. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long
as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed transitioned
between.
5. Duty cycle reference is LVDD/2.
6. This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention.
GTX_CLK supply voltage is fixed at 3.3V inside the chip. If PHY supplies a 2.5 V Clock signal on this input, set TSCOMOBI
bit of System I/O configuration register (SICRH) as 1. See the
MPC8315E PowerQUICC II Pro Integrated Host Processor
Family Reference Manual.
REF_CLK
RXD[1:0]
tRMRDXKH
tRMX
tRMXH
tRMXR
tRMXF
CRS_DV
RX_ER
tRMRDVKH
Valid Data
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| MPC8315 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MPC8315E PowerQUICC II Pro Processor Hardware Specifications |
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