參數(shù)資料
型號: MPC8314EVRAGDA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: MICROPROCESSOR, PBGA620
封裝: 29 X 29 MM, LEAD FREE, PLASTIC, TEPBGA-620
文件頁數(shù): 59/106頁
文件大小: 1253K
代理商: MPC8314EVRAGDA
MPC8314E PowerQUICC II Pro Processor Hardware Specifications, Rev. 0
56
Freescale Semiconductor
High-Speed Serial Interfaces (HSSI)
Many other low voltage differential type outputs like LVDS (Low Voltage Differential Signaling) can be
used but may need to be AC-coupled due to the limited common mode input range allowed (100 to 400
mV) for DC-coupled connection.
LVPECL outputs can produce signal with too large amplitude and may need to be DC-biased at clock
driver output first, then followed with series attenuation resistor to reduce the amplitude, in addition to
AC-coupling.
NOTE
Figure 42 to Figure 45 below are for conceptual reference only. Due to the
fact that clock driver chip's internal structure, output impedance and
termination requirements are different between various clock driver chip
manufacturers, it’s very possible that the clock circuit reference designs
provided by clock driver chip vendor are different from what is shown
below. They might also vary from one vendor to the other. Therefore,
Freescale Semiconductor can neither provide the optimal clock driver
reference circuits, nor guarantee the correctness of the following clock
driver connection reference circuits. The system designer is recommended
to contact the selected clock driver chip vendor for the optimal reference
circuits with the MPC8315E SerDes reference clock receiver requirement
provided in this document.
Figure 42 shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It
assumes that the DC levels of the clock driver chip is compatible with MPC8315E SerDes reference clock
input’s DC requirement.
Figure 42. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only)
Figure 43 shows the SerDes reference clock connection reference circuits for LVDS type clock driver.
Since LVDS clock driver’s common mode voltage is higher than the MPC8315E SerDes reference clock
input’s allowed range (100 to 400mV), AC-coupled connection scheme must be used. It assumes the
50
Ω
50
Ω
SD_REF_CLK
Clock Driver
100
Ω differential PWB trace
Clock driver vendor dependent
source termination resistor
SerDes Refer.
CLK Receiver
Clock Driver
CLK_Out
HCSL CLK Driver Chip
33
Ω
33
Ω
Total 50
Ω. Assume clock driver’s
output impedance is about 16
Ω.
MPC8315E
CLK_Out
相關(guān)PDF資料
PDF描述
MPC8315EVRAFDA 32-BIT, 333 MHz, MICROPROCESSOR, PBGA620
MPC8315EVRADDA 32-BIT, 266 MHz, MICROPROCESSOR, PBGA620
MPC8315EVRAGDA 32-BIT, 400 MHz, MICROPROCESSOR, PBGA620
MPC8315VRAFDA 32-BIT, 333 MHz, MICROPROCESSOR, PBGA620
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