- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45360 > MPC8315VRAFDA (FREESCALE SEMICONDUCTOR INC) 32-BIT, 333 MHz, MICROPROCESSOR, PBGA620 PDF資料下載
參數(shù)資料
| 型號(hào)： | MPC8315VRAFDA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 333 MHz, MICROPROCESSOR, PBGA620 |
| 封裝： | 29 X 29 MM, 2.23 MM HEIGHT, 1 MM PITCH, LEAD FREE, TEPBGAII-620 |
| 文件頁數(shù)： | 28/112頁 |
| 文件大?。?/td> | 1283K |
| 代理商： | MPC8315VRAFDA |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁當(dāng)前第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁
MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 0
22
Freescale Semiconductor
DDR and DDR2 SDRAM
7.2.2
DDR and DDR2 SDRAM Output AC Timing Specifications
Table 20. DDR and DDR2 SDRAM Output AC Timing Specifications
At recommended operating conditions
Parameter
Symbol 1
Min
Max
Unit
Notes
MCK[n] cycle time at MCK[n]/MCK[n] crossing
tMCK
7.5
10
ns
2
ADDR/CMD output setup with respect to MCK
266 MHz
200 MHz
tDDKHAS
2.9
3.5
—
ns
3
ADDR/CMD output hold with respect to MCK
266 MHz
200 MHz
tDDKHAX
3.15
4.20
—
ns
3
MCS[n] output setup with respect to MCK
266 MHz
200 MHz
tDDKHCS
3.15
4.20
—
ns
3
MCS[n] output hold with respect to MCK
266 MHz
200 MHz
tDDKHCX
3.15
4.20
—
ns
3
MCK to MDQS Skew
tDDKHMH
–0.6
0.6
ns
4
MDQ//MDM output setup with respect to MDQS
266 MHz
200 MHz
tDDKHDS,
tDDKLDS
900
1000
—
ps
5
MDQ//MDM output hold with respect to MDQS
266 MHz
200 MHz
tDDKHDX,
tDDKLDX
1100
1200
—
ps
5
MDQS preamble start
tDDKHMP
–0.5
× tMCK – 0.6 –0.5 × tMCK + 0.6
ns
6
MDQS epilogue end
tDDKHME
–0.6
0.6
ns
6
Note:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until
outputs (A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock
reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ//MDM/MDQS.
4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing
(DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through
control of the DQSS override bits in the TIMING_CFG_2 register. This is typically set to the same delay as the clock adjust
in the CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the
same adjustment value. See the
MPC8315E PowerQUICC II Pro Host Processor Reference Manual for a description and
understanding of the timing modifications enabled by use of these bits.
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC (),
or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.
6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that tDDKHMP follows the
symbol conventions described in note 1.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC8321EVRAFDCA | 32-BIT, 333 MHz, RISC PROCESSOR, PBGA516 |
| MPC8321EZQADDCA | 32-BIT, 266 MHz, RISC PROCESSOR, PBGA516 |
| MPC8321VRAFDCA | 32-BIT, 333 MHz, RISC PROCESSOR, PBGA516 |
| MPC8321EVRADDCA | 32-BIT, 266 MHz, RISC PROCESSOR, PBGA516 |
| MPC8321CVRADDCA | 32-BIT, 266 MHz, RISC PROCESSOR, PBGA516 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC8315VRAGD | 制造商:Freescale Semiconductor 功能描述:MPC8315VRAGD - Bulk |
| MPC8315VRAGDA | 功能描述:微處理器 - MPU NON-ENCRYPT RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8321CVRADDC | 功能描述:微處理器 - MPU 8321 NOPB PBGA W/O ENCR RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8321CVRADDC | 制造商:Freescale Semiconductor 功能描述:Embedded Networking Processor |
| MPC8321CVRAFDC | 功能描述:微處理器 - MPU 8321 NOPB PBGA W/O ENCR RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。