參數(shù)資料
型號(hào): MPC8315VRAFDA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 333 MHz, MICROPROCESSOR, PBGA620
封裝: 29 X 29 MM, 2.23 MM HEIGHT, 1 MM PITCH, LEAD FREE, TEPBGAII-620
文件頁(yè)數(shù): 45/112頁(yè)
文件大?。?/td> 1283K
代理商: MPC8315VRAFDA
MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 0
38
Freescale Semiconductor
Ethernet: Three-Speed Ethernet, MII Management
9.5.4.2
SGMII Receive AC Timing Specifications
Table 38 provides the SGMII receive AC timing specifications. Source synchronous clocking is not
supported. Clock is recovered from the data. Figure 20 shows the SGMII Receiver Input Compliance
Mask eye diagram.
Table 38. SGMII Receive AC Timing Specifications
At recommended operating conditions with XCOREVDD = 1.0V ± 5%.
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Deterministic Jitter Tolerance
JD
0.37
UI p-p
1
Combined Deterministic and Random Jitter Tolerance
JDR
0.55
UI p-p
1
Sinusoidal Jitter Tolerance
JSIN
0.1
UI p-p
1
Total Jitter Tolerance
JT
0.65
UI p-p
1
Bit Error Ratio
BER
10-12
Unit Interval
UI
799.92
800
800.08
ps
2
AC Coupling Capacitor
CTX
5
200
nF
3
Notes:
1. Measured at receiver.
2. Each UI is 800 ps ± 100 ppm.
3. The external AC coupling capacitor is required. It’s recommended to be placed near the device transmitter outputs.
4. Refer to RapidIOTM 1x/4x LP Serial Physical Layer Specification for interpretation of jitter specifications.
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