參數(shù)資料
型號(hào): MPC8323EZQADDC
廠商: Freescale Semiconductor
文件頁數(shù): 12/82頁
文件大?。?/td> 0K
描述: IC MPU PWRQUICC II 516-PBGA
產(chǎn)品培訓(xùn)模塊: MPC8323E PowerQUICC II Pro Processor
標(biāo)準(zhǔn)包裝: 40
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 266MHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 516-BBGA
供應(yīng)商設(shè)備封裝: 516-FPBGA(27x27)
包裝: 托盤
配用: MPC8323E-RDB-ND - BOARD REFERENCE DESIGN
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
2
Freescale Semiconductor
Overview
1Overview
The MPC8323E incorporates the e300c2 (MPC603e-based) core built on Power Architecture
technology, which includes 16 Kbytes of L1 instruction and data caches, dual integer units, and on-chip
memory management units (MMUs). The e300c2 core does not contain a floating point unit (FPU). The
MPC8323E also includes a 32-bit PCI controller, four DMA channels, a security engine, and a 32-bit
DDR1/DDR2 memory controller.
A new communications complex based on QUICC Engine technology forms the heart of the networking
capability of the MPC8323E. The QUICC Engine block contains several peripheral controllers and a
32-bit RISC controller. Protocol support is provided by the main workhorses of the device—the unified
communication controllers (UCCs). Note that the MPC8321 and MPC8321E do not support UTOPIA. A
block diagram of the MPC8323E is shown in Figure 1.
Figure 1. MPC8323E Block Diagram
Each of the five UCCs can support a variety of communication protocols: 10/100 Mbps Ethernet, serial
ATM, HDLC, UART, and BISYNC—and, in the MPC8323E and MPC8323, multi-PHY ATM and ATM
support for up to OC-3 speeds.
Local
Baud Rate
Generators
Parallel I/O
Accelerators
Single 32-Bit RISC CP
3 MII/RMII
4 TDM Ports
1 UL2/8-Bit
QUICC Engine Block
Security Engine (SEC 2.2)
PCI
DDR
UCC
4
UCC
3
UCC
2
UCC
1
Multi-User
RAM
Serial DMA
and
2 Virtual
DMAs
Serial Interface
UCC
5
SPI
Time Slot Assigner
SPI
MPC8323E
USB
System Interface Unit
(SIU)
System Reset
Clock Synthesizer
Protection and Configuration
Interrupt Controller
4 Channel DMA
Bus Arbitration
DUART
I2C
PCI Controller
Local Bus
Memory Controllers
GPCM/UPM
32-Bit DDR1/DDR2
Interface Unit
Timers, Power Management,
and JTAG/COP
16 KB
D-Cache
16 KB
I-Cache
e300c2 Core
Integer Unit
(IU1)
Integer Unit
(IU2)
Classic G2 MMUs
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