參數(shù)資料
型號: MPC8323EZQADDC
廠商: Freescale Semiconductor
文件頁數(shù): 64/82頁
文件大?。?/td> 0K
描述: IC MPU PWRQUICC II 516-PBGA
產(chǎn)品培訓模塊: MPC8323E PowerQUICC II Pro Processor
標準包裝: 40
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 266MHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 516-BBGA
供應商設備封裝: 516-FPBGA(27x27)
包裝: 托盤
配用: MPC8323E-RDB-ND - BOARD REFERENCE DESIGN
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
Freescale Semiconductor
67
Clocking
22.4
System PLL Configuration
The system PLL is controlled by the RCWL[SPMF] parameter. Table 58 shows the multiplication factor
encodings for the system PLL.
NOTE
System PLL VCO frequency = 2 × (CSB frequency) × (System PLL VCO
divider).
The VCO divider needs to be set properly so that the System PLL VCO
frequency is in the range of 300–600 MHz.
As described in Section 22, “Clocking,the LBCM, DDRCM, and SPMF parameters in the reset
configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the
primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk). Table 59
DDR1/DDR2 memory bus frequency (MCLK)2
133
MHz
Local bus frequency (LCLK
n)3
66
MHz
PCI input frequency (CLKIN or PCI_CLK)
66
MHz
1 The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the resulting csb_clk, MCLK,
LCLK[0:2], and
core_clk frequencies do not exceed their respective maximum or minimum operating frequencies.
2 The DDR1/DDR2 data rate is 2× the DDR1/DDR2 memory bus frequency.
3 The local bus frequency is 1/2, 1/4, or 1/8 of the lb_clk frequency (depending on LCRR[CLKDIV]) which is in turn 1× or 2× the
csb_clk frequency (depending on RCWL[LBCM]).
Table 58. System PLL Multiplication Factors
RCWL[SPMF]
System PLL
Multiplication Factor
0000
Reserved
0001
Reserved
0010
× 2
0011
× 3
0100
× 4
0101
× 5
0110
× 6
0111–1111
Reserved
Table 57. Operating Frequencies for PBGA (continued)
Characteristic1
Max Operating Frequency
Unit
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