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| 型號： | MPC8343CVRADDX |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 266 MHz, MICROPROCESSOR, PBGA620 |
| 封裝： | 29 X 29 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-620 |
| 文件頁數(shù)： | 9/92頁 |
| 文件大?。?/td> | 987K |
| 代理商： | MPC8343CVRADDX |
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MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
17
DDR SDRAM
MDQS preamble start
tDDKHMP
-0.25
× t
MCK – 0.9
-0.25
× t
MCK +0.3
ns
7
MDQS epilogue end
tDDKLME
-0.9
0.3
ns
7
Notes:
1.
The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can
be read as DDR timing (DD) from the rising or falling edge of the reference clock (KH or KL) until the output went
invalid (AX or DX). For example, tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference
(K) goes from the high (H) state until outputs (A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR
timing (DD) for the time tMCK memory clock reference (K) goes low (L) until data outputs (D) are invalid (X) or data
output hold time.
2.
All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3.
In the source synchronous mode, MCK/MCK can be shifted in 1/4 applied cycle increments through the Clock
Control Register. For the skew measurements referenced for tAOSKEW it is assumed that the clock adjustment is set
to align the address/command valid with the rising edge of MCK.
4.
ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS.
For the ADDR/CMD setup and hold specifications, it is assumed that the Clock Control register is set to adjust the
memory clocks by 1/2 applied cycle.
5.
Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR
timing (DD) from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be
modified through control of the DQSS override bits in the TIMING_CFG_2 register. In source synchronous mode,
this will typically be set to the same delay as the clock adjust in the CLK_CNTL register. The timing parameters listed
in the table assume that these 2 parameters have been set to the same adjustment value. See the
MPC8349E
Integrated Host Processor Preliminary Reference Manual Rev.0 for a description and understanding of the
timing modifications enabled by use of these bits.
6.
Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data
(MDQ), ECC (MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins
of the MPC8343E.
7.
All outputs are referenced to the rising edge of MCK(n) at the pins of the MPC8343E. Note that tDDKHMP follows
the symbol conventions described in note 1.
Table 11. DDR SDRAM Output AC Timing Specifications for Source Synchronous Mode (continued)
At recommended operating conditions with GVDD of 2.5 V ± 5%.
Parameter
Symbol 1
Min
Max
Unit
Notes
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| MPC8343CVRAGD | 功能描述:IC MPU PWRQUICC II PRO 620-PBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:MPC83xx 標(biāo)準(zhǔn)包裝:1 系列:MPC85xx 處理器類型:32-位 MPC85xx PowerQUICC III 特點:- 速度:1.2GHz 電壓:1.1V 安裝類型:表面貼裝 封裝/外殼:783-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:783-FCPBGA（29x29） 包裝:托盤 |
| MPC8343CVRAGDB | 功能描述:微處理器 - MPU 8347 PBGA NO-PB W/O ENCR RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8343CZQADD | 功能描述:IC MPU PWRQUICC II PRO 620-PBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:MPC83xx 標(biāo)準(zhǔn)包裝:1 系列:MPC85xx 處理器類型:32-位 MPC85xx PowerQUICC III 特點:- 速度:1.2GHz 電壓:1.1V 安裝類型:表面貼裝 封裝/外殼:783-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:783-FCPBGA（29x29） 包裝:托盤 |
| MPC8343CZQADDB | 功能描述:微處理器 - MPU 8347 PBGA W/O ENC W/ PB RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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