參數(shù)資料
型號(hào)： MPC8349ECVVALD
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 667 MHz, MICROPROCESSOR, PBGA672
封裝： 35 X 35 MM, 1.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, TBGA-672
文件頁(yè)數(shù)： 48/88頁(yè)
文件大小： 1014K
代理商： MPC8349ECVVALD
MPC8349E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10
52
Freescale Semiconductor
SPI
17 SPI
This section describes the SPI DC and AC electrical specifications.
17.1
SPI DC Electrical Characteristics
Table 49 provides the SPI DC electrical characteristics.
17.2
SPI AC Timing Specifications
Table 50 provides the SPI input and output AC timing specifications.
Table 49. SPI DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Input high voltage
VIH
2.0
OVDD +0.3
V
Input low voltage
VIL
–0.3
0.8
V
Input current
IIN
±5
μA
Output high voltage
VOH
IOH = –8.0 mA
2.4
—
V
Output low voltage
VOL
IOL = 8.0 mA
—
0.5
V
Output low voltage
VOL
IOL = 3.2 mA
—
0.4
V
Table 50. SPI AC Timing Specifications1
Characteristic
Symbol2
Min
Max
Unit
SPI outputs valid—Master mode (internal clock) delay
tNIKHOV
6ns
SPI outputs hold—Master mode (internal clock) delay
tNIKHOX
0.5
ns
SPI outputs valid—Slave mode (external clock) delay
tNEKHOV
8ns
SPI outputs hold—Slave mode (external clock) delay
tNEKHOX
2ns
SPI inputs—Master mode (internal clock input setup time
tNIIVKH
4ns
SPI inputs—Master mode (internal clock input hold time
tNIIXKH
0ns
SPI inputs—Slave mode (external clock) input setup time
tNEIVKH
4ns
SPI inputs—Slave mode (external clock) input hold time
tNEIXKH
2ns
Notes:
1. Output specifications are measured from the 50 percent level of the rising edge of CLKIN to the 50 percent level of the signal.
Timings are measured at the pin.
2. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOX symbolizes the internal timing
(NI) for the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X).
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