參數(shù)資料
型號(hào): MPC8349ECVVALD
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 667 MHz, MICROPROCESSOR, PBGA672
封裝: 35 X 35 MM, 1.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, TBGA-672
文件頁(yè)數(shù): 82/88頁(yè)
文件大小: 1014K
代理商: MPC8349ECVVALD
MPC8349E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
83
Document Revision History
22 Document Revision History
Table 62 provides a revision history of this document.
Table 62. Document Revision History
Revision
Date
Substantive Change(s)
10
4/2007
In Table 3, “Output Drive Capability,” changed the values in the Output Impedance column and added
USB to the seventh row.
In Section 21.7, “Pull-Up Resistor Requirements,deleted last two paragraphs and after first
paragraph, added a new paragraph.
Deleted Section 21.8, “JTAG Configuration Signals,” and Figure 43, “JTAG Interface Connection.”
9
3/2007
In Table 53, “Operating Frequencies for TBGA,” in the ‘Coherent system bus frequency (
csb_clk)’ row,
changed the value in the 533 MHz column to 100-333.
In Table 58, “Suggested PLL Configurations,” under the subhead, ‘33 MHz CLKIN/PCI_CLK Options,’
added row A03 between Ref. No. 724 and 804. Under the subhead ‘66 MHz CLKIN/PCI_CLK
Options,’ added row 503 between Ref. No. 305 and 404. For Ref. No. 306, changed the CORE PLL
value to 0000110.
In Section 23, “Ordering Information,” replaced first paragraph and added a note.
In Section 23.1, “Part Numbers Fully Addressed by This Document,” replaced first paragraph.
8
2/2007
Page 1, updated first paragraph to reflect PowerQUICC II Pro information. Updated note after second
paragraph.
In the features list in Section 1, “Overview,” corrected DDR data rate to show:
333 MHz for DDR for TBGA parts for silicon Rev. 1.x
In Figure 42, “JTAG Interface Connection,” updated with new figure.
In Section 23, “Ordering Information,” replicated note from introduction.
In Section 23.1, “Part Numbers Fully Addressed by This Document,” replaced third sentence of first
paragraph directing customer to product summary page for available frequency configuration parts.
Updated back page information.
7
8/2006
Changed all references to revision 2.0 silicon to revision 3.0 silicon.
Changed VIH minimum value in Table 40, “JTAG Interface DC Electrical Characteristics,” to
OVDD –0.3.
In Table 66, “Suggested PLL Configurations,” deleted reference-number rows 902 and 703.
6
3/2006
Section 2, “Electrical Characteristics,” moved to second section and all other section, table, and figure
numbering change accordingly.
Table 8, “CLKIN AC Timing Specifications:” Changed max rise and fall time from 1.2 to 2.3.
Table 26, “GMII Receive AC Timing Specifications:” Changed min tTTKHDX from 0.5 to 1.0.
Table 34, “MII Management AC Timing Specifications:” Changed max value of tMDKHDX from 70 to
170.
Table 38, “Local Bus General Timing Parameters—DLL on:” Changed min tLBIVKH2 from 1.7 to 2.2.
Table 40, “JTAG interface DC Electrical Characteristics:” Changed VIH input high voltage min to 2.0.
Table 51, “Operating Frequencies for TBGA:”
Updated TBD values.
Changed maximum coherent system bus frequency for TBGA 533-MHz device to 266.
Added Section 23.2, “Part Marking.”
Table 58, “Suggested PLL Configurations:” Removed some values from suggested PLL
configurations for reference numbers 902, 922, 903, and 923.
Table 65, “Part Numbering Nomenclature:” Updated TBD values in note 1.
Added Table 66 “SVR Settings.”
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