參數(shù)資料
型號: MPC8533VTAQGA
廠商: Freescale Semiconductor
文件頁數(shù): 11/112頁
文件大?。?/td> 0K
描述: MPU POWERQUICC 783-PBGA
標(biāo)準(zhǔn)包裝: 36
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.0GHz
電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 6
108
Freescale Semiconductor
System Design Information
21.10 Guidelines for High-Speed Interface Termination
This section provides guidelines for when the SerDes interface is either not used at all or only partly used.
21.10.1 SerDes Interface Entirely Unused
If the high-speed SerDes interface is not used at all, the unused pin should be terminated as described in
this section. However, the SerDes must always have power applied to its supply pins.
The following pins must be left unconnected (float):
SD_TX[0:7]
The following pins must be connected to GND:
SD_RX[0:7]
SD_REF_CLK
SD_REF_CLK
21.10.2 SerDes Interface Partly Unused
If only part of the high speed SerDes interface pins are used, the remaining high-speed serial I/O pins
should be terminated as described in this section.
The following pins must be left unconnected (float) if not used:
SD_TX[0:7]
The following pins must be connected to GND if not used:
SD_RX[0:7]
SD_REF_CLK
SD_REF_CLK
21.11 Guideline for PCI Interface Termination
PCI termination, if not used at all, is done as follows.
Option 1
If PCI arbiter is enabled during POR,
All AD pins will be driven to the stable states after POR. Therefore, all ADs pins can be floating.
All PCI control pins can be grouped together and tied to OVDD through a single 10-k resistor.
It is optional to disable PCI block through DEVDISR register after POR reset.
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