參數(shù)資料
型號: MPC8535CVTAQGA
廠商: Freescale Semiconductor
文件頁數(shù): 64/126頁
文件大小: 0K
描述: MCU PWRQUICC II 1000MHZ 783-PBGA
標(biāo)準(zhǔn)包裝: 1
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.0GHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
其它名稱: MPC8535CVTAQG
MPC8535CVTAQG-ND
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Electrical Characteristics
Freescale Semiconductor
42
Timing diagrams for FIFO appear in the following figures.
Figure 14. FIFO Transmit AC Timing Diagram
Rise time TX_CLK (20%–80%)
tFITR
0.75
ns
Fall time TX_CLK (80%–20%)
tFITF
0.75
ns
GTX_CLK to FIFO data TXD[7:0], TX_ER, TX_EN hold time
tFITDX
1
0.5
3.0
ns
Note:
1. Data valid tFITDV to GTX_CLK Min Setup time is a function of clock period and max hold time. (Min Setup = Cycle time
– Max Hold)
2. The minimum cycle period (or maximum frequency) of the RX_CLK is dependent on the maximum platform frequency
of the speed bins the part belongs to as well as the FIFO mode under operation. See Section 2.4.6, “Platform to FIFO
Restrictions,” for more detailed description.
Table 27. FIFO Mode Receive AC Timing Specification
Parameter/Condition
Symbol
Min
Typ
Max
Unit
RX_CLK clock period1
tFIR
6.0
8.0
100
ns
RX_CLK duty cycle
tFIRH/tFIRH
45
50
55
%
RX_CLK peak-to-peak jitter
tFIRJ
——
250
ps
Rise time RX_CLK (20%–80%)
tFIRR
0.75
ns
Fall time RX_CLK (80%–20%)
tFIRF
0.75
ns
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
tFIRDV
1.5
——ns
RXD[7:0], RX_DV, RX_ER hold time to RX_CLK
tFIRDX
0.5
——ns
Note:
1. The minimum cycle period (or maximum frequency) of the RX_CLK is dependent on the maximum platform frequency
of the speed bins the part belongs to as well as the FIFO mode under operation. See Section 2.4.6, “Platform to FIFO
Restrictions,” for more detailed description.
Table 26. FIFO Mode Transmit AC Timing Specification (continued)
Parameter/Condition
Symbol
Min
Typ
Max
Unit
tFIT
tFITH
tFITF
tFITDX
TXD[7:0]
TX_EN
GTX_CLK
TX_ER
tFITDV
tFITR
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