參數(shù)資料
型號: MPC8535CVTAQGA
廠商: Freescale Semiconductor
文件頁數(shù): 77/126頁
文件大?。?/td> 0K
描述: MCU PWRQUICC II 1000MHZ 783-PBGA
標(biāo)準(zhǔn)包裝: 1
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.0GHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
其它名稱: MPC8535CVTAQG
MPC8535CVTAQG-ND
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Electrical Characteristics
Freescale Semiconductor
54
When operating in SGMII mode, the eTSEC EC_GTX_CLK125 clock is not required for this port. Instead, SerDes reference
clock is required on SD2_REF_CLK and SD2_REF_CLK pins.
2.9.3.1
DC Requirements for SGMII SD2_REF_CLK and SD2_REF_CLK
The characteristics and DC requirements of the separate SerDes reference clock are described in Section 2.20, “High-Speed
2.9.3.2
AC Requirements for SGMII SD2_REF_CLK and SD2_REF_CLK
This table lists the SGMII SerDes reference clock AC requirements. Please note that SD2_REF_CLK and SD2_REF_CLK are
not intended to be used with, and should not be clocked by, a spread spectrum clock source.
Table 38. SD2_REF_CLK and SD2_REF_CLK AC Requirements
Symbol
Parameter Description
Min
Typical
Max
Units Notes
tREF
REFCLK cycle time
10 (8)
ns
1
tREFCJ REFCLK cycle-to-cycle jitter. Difference in the period of any two adjacent
REFCLK cycles
100
ps
tREFPJ Phase jitter. Deviation in edge location with respect to mean edge location
–50
50
ps
2,3
Notes:
1. 8 ns applies only when 125 MHz SerDes2 reference clock frequency is selected via cfg_srds_sgmii_refclk during POR.
2. In a frequency band from 150 kHz to 15 MHz, at BER of 10E-12.
3. Total peak-to-peak deterministic jitter “Dj” should be less than or equal to 50 ps.
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