參數(shù)資料
型號: MPC8544EAVTALF
廠商: Freescale Semiconductor
文件頁數(shù): 107/117頁
文件大小: 0K
描述: IC MPU POWERQUICC III 783-FCBGA
產(chǎn)品培訓模塊: MPC8544E PowerQUICC™ III
標準包裝: 1
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 667MHz
電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
配用: MPC8544DS-ND - BOARD DEVELOPMENT SYSTEM 8544
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
9
Electrical Characteristics
2.1.2
Recommended Operating Conditions
Table 2 provides the recommended operating conditions for this device. Note that the values in Table 2 are
the recommended and tested operating conditions. Proper device operation outside these conditions is not
guaranteed.
DDR and DDR2 DRAM I/O voltage
GVDD
–0.3 to 2.75
–0.3 to 1.98
V—
Three-speed Ethernet I/O, MII management voltage
LVDD (eTSEC1)
–0.3 to 3.63
–0.3 to 2.75
V—
TVDD (eTSEC3)
–0.3 to 3.63
–0.3 to 2.75
V—
PCI, DUART, system control and power management, I2C, and
JTAG I/O voltage
OVDD
–0.3 to 3.63
V
Local bus I/O voltage
BVDD
–0.3 to 3.63
–0.3 to 2.75
–0.3 to 1.98
V—
Input voltage
DDR/DDR2 DRAM signals
MVIN
–0.3 to (GVDD + 0.3)
V
2
DDR/DDR2 DRAM reference
MVREF
–0.3 to (GVDD + 0.3)
V
2
Three-speed Ethernet signals
LVIN
TVIN
–0.3 to (LVDD + 0.3)
–0.3 to (TVDD + 0.3)
V2
Local bus signals
BVIN
–0.3 to (BVDD + 0.3)
V
DUART, SYSCLK, system control and power
management, I2C, and JTAG signals
OVIN
–0.3 to (OVDD + 0.3)
V
2
PCI
OVIN
–0.3 to (OVDD + 0.3)
V
2
Storage temperature range
TSTG
–55 to 150
° C—
Notes:
1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause.
2. (M,L,O)VIN, and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
Table 2. Recommended Operating Conditions
Characteristic
Symbol
Recommended
Value
Unit
Notes
Core supply voltage
VDD
1.0 ± 50 mV
V
PLL supply voltage
AVDD
1.0 ± 50 mV
V
1
Core power supply for SerDes transceivers
SVDD
1.0 ± 50 mV
V
Pad power supply for SerDes transceivers
XVDD
1.0 ± 50 mV
V
DDR and DDR2 DRAM I/O voltage
GVDD
2.5 V ± 125 mV
1.8 V ± 90 mV
V2
Table 1. Absolute Maximum Ratings1 (continued)
Characteristic
Symbol
Max Value
Unit
Notes
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