參數(shù)資料
型號: MPC8547VUAUG
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 1000 MHz, MICROPROCESSOR, CBGA783
封裝: 29 X 29 MM, 1 MM PITCH, FLIP CHIP, LEAD FREE, CERAMIC, BGA-783
文件頁數(shù): 28/142頁
文件大?。?/td> 1504K
代理商: MPC8547VUAUG
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
123
Clocking
Table 73. Processor Core Clocking Specifications (MPC8543E)
Characteristic
Maximum Processor Core Frequency
Unit
Notes
800 MHz
1000 MHz
Min
Max
Min
Max
e500 core processor frequency
800
1000
MHz
1, 2
Notes:
1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK
frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating
frequencies. Refer to Section 19.2, “CCB/SYSCLK PLL Ratio,and Section 19.3, “e500 Core PLL Ratio,for ratio settings.
2.)The minimum e500 core frequency is based on the minimum platform frequency of 333 MHz.
Table 74. Memory Bus Clocking Specifications (MPC8548E and MPC8547E)
Characteristic
Maximum Processor Core Frequency
Unit
Notes
1000, 1200, 1333 MHz
Min
Max
Memory bus clock speed
166
266
MHz
1, 2
Notes:
1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting
SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum
operating frequencies. Refer to Section 19.2, “CCB/SYSCLK PLL Ratio,and Section 19.3, “e500 Core PLL Ratio,for ratio
settings.
2. The memory bus speed is half of the DDR/DDR2 data rate, hence, half of the platform clock frequency.
Table 75. Memory Bus Clocking Specifications (MPC8545E)
Characteristic
Maximum Processor Core Frequency
Unit
Notes
800, 1000, 1200 MHz
Min
Max
Memory bus clock speed
166
200
MHz
1, 2
Notes:
1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting
SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum
operating frequencies. Refer to Section 19.2, “CCB/SYSCLK PLL Ratio,and Section 19.3, “e500 Core PLL Ratio,for ratio
settings.
2. The memory bus speed is half of the DDR/DDR2 data rate, hence, half of the platform clock frequency.
相關(guān)PDF資料
PDF描述
MPC8548CHXAVHB 32-BIT, 1500 MHz, MICROPROCESSOR, CBGA783
MPC8548CPXAVJ 32-BIT, 1500 MHz, MICROPROCESSOR, PBGA783
MPC8548CVTAVGB 32-BIT, 1500 MHz, MICROPROCESSOR, PBGA783
MPC8548CVUAUHB 32-BIT, 1333 MHz, MICROPROCESSOR, CBGA783
MPC8548CVUAVHB 32-BIT, 1500 MHz, MICROPROCESSOR, CBGA783
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