參數(shù)資料
型號(hào): MPC8547VUAUG
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 1000 MHz, MICROPROCESSOR, CBGA783
封裝: 29 X 29 MM, 1 MM PITCH, FLIP CHIP, LEAD FREE, CERAMIC, BGA-783
文件頁數(shù): 83/142頁
文件大?。?/td> 1504K
代理商: MPC8547VUAUG
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
45
Local Bus
Figure 23 through Figure 28 show the local bus signals.
Figure 23. Local Bus Signals (PLL Enabled)
Table 42 describes the timing parameters of the local bus interface at BVDD = 3.3 V with PLL disabled.
Table 42. Local Bus Timing Parameters—PLL Bypassed
Parameter
Symbol1
Min
Max
Unit
Notes
Local bus cycle time
tLBK
12
ns
2
Local bus duty cycle
tLBKH/tLBK
43
57
%
Internal launch/capture clock to LCLK delay
tLBKHKT
2.3
4.4
ns
8
Input setup to local bus clock (except LGTA/LUPWAIT)
tLBIVKH1
6.2
ns
4, 5
LGTA/LUPWAIT input setup to local bus clock
tLBIVKL2
6.1
ns
4, 5
Input hold from local bus clock (except LGTA/LUPWAIT)
tLBIXKH1
–1.8
ns
4, 5
LGTA/LUPWAIT input hold from local bus clock
tLBIXKL2
–1.3
ns
4, 5
LALE output transition to LAD/LDP output transition (LATCH hold time)
tLBOTOT
1.5
ns
6
Local bus clock to output valid (except LAD/LDP and LALE)
tLBKLOV1
–0.3
ns
Output Signals:
LA[27:31]/LBCTL/LBCKE/LOE/
LSDA10/LSDWE/LSDRAS/
LSDCAS/LSDDQM[0:3]
tLBKHOV1
tLBKHOV2
tLBKHOV3
LSYNC_IN
Input Signals:
LAD[0:31]/LDP[0:3]
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
Output (Address) Signal:
LAD[0:31]
LALE
tLBIXKH1
tLBIVKH1
tLBIVKH2
tLBIXKH2
tLBKHOX1
tLBKHOZ1
tLBKHOX2
tLBKHOZ2
Input Signal:
LGTA
tLBOTOT
tLBKHOZ2
tLBKHOX2
tLBKHOV4
LUPWAIT
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