參數(shù)資料
型號: MPC8547VUAUG
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 1000 MHz, MICROPROCESSOR, CBGA783
封裝: 29 X 29 MM, 1 MM PITCH, FLIP CHIP, LEAD FREE, CERAMIC, BGA-783
文件頁數(shù): 85/142頁
文件大?。?/td> 1504K
代理商: MPC8547VUAUG
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
47
Local Bus
Figure 24. Local Bus Signals (PLL Bypass Mode)
NOTE
In PLL bypass mode, LCLK[n] is the inverted version of the internal clock
with the delay of tLBKHKT. In this mode, signals are launched at the rising edge
of the internal clock and are captured at falling edge of the internal clock
with the exception of LGTA/LUPWAIT (which is captured on the rising
edge of the internal clock).
Output Signals:
LA[27:31]/LBCTL/LBCKE/LOE/
LSDA10/LSDWE/LSDRAS/
LSDCAS/LSDDQM[0:3]
tLBKLOV2
LCLK[
n]
Input Signals:
LAD[0:31]/LDP[0:3]
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
LALE
tLBIXKH1
Input Signal:
LGTA
Output (Address) Signal:
LAD[0:31]
tLBIVKH1
tLBIXKL2
tLBIVKL2
tLBKLOX1
tLBKLOZ2
tLBOTOT
Internal Launch/Capture Clock
tLBKLOX2
tLBKLOV1
tLBKLOV3
tLBKLOZ1
tLBKHKT
tLBKLOV4
LUPWAIT
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