參數(shù)資料
型號(hào): MPC8548ECPXAUJB
廠商: Freescale Semiconductor
文件頁數(shù): 88/151頁
文件大?。?/td> 0K
描述: MPU POWERQUICC III 783-PBGA
產(chǎn)品培訓(xùn)模塊: MPC8548 PowerQUICC III Processors
標(biāo)準(zhǔn)包裝: 1
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.333GHz
電壓: 1.1V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
Freescale Semiconductor
41
Ethernet Management Interface Electrical Characteristics
9
Ethernet Management Interface Electrical
Characteristics
The electrical characteristics specified here apply to MII management interface signals MDIO
(management data input/output) and MDC (management data clock). The electrical characteristics for
GMII, RGMII, RMII, TBI, and RTBI are specified in “Section 8, “Enhanced Three-Speed Ethernet
9.1
MII Management DC Electrical Characteristics
The MDC and MDIO are defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics
for MDIO and MDC are provided in this table.
9.2
MII Management AC Electrical Specifications
This table provides the MII management AC timing specifications.
Table 36. MII Management DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
Supply voltage (3.3 V)
OVDD
3.13
3.47
V
Output high voltage (OVDD = Min, IOH = –1.0 mA)
VOH
2.10
OVDD + 0.3
V
Output low voltage (OVDD =Min, IOL = 1.0 mA)
VOL
GND
0.50
V
Input high voltage
VIH
2.0
V
Input low voltage
VIL
—0.90
V
Input high current (OVDD = Max, VIN
1 = 2.1 V)
IIH
—40
A
Input low current (OVDD = Max, VIN = 0.5 V)
IIL
–600
A
Note:
1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.
Table 37. MII Management AC Timing Specifications
At recommended operating conditions with OVDD is 3.3 V ± 5%.
Parameter
Symbol1
Min
Typ
Max
Unit
Notes
MDC frequency
fMDC
0.72
2.5
8.3
MHz
2, 3, 4
MDC period
tMDC
120.5
1389
ns
MDC clock pulse width high
tMDCH
32
ns
MDC to MDIO valid
tMDKHDV
16
t
CCB
——
ns
5
MDC to MDIO delay
tMDKHDX
(16 × tCCB× 8) – 3
(16 × tCCB × 8) + 3
ns
5
MDIO to MDC setup time
tMDDVKH
5—
ns
MDIO to MDC hold time
tMDDXKH
0—
ns
MDC rise time
tMDCR
——
10
ns
4
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