參數(shù)資料
型號(hào): MPC8548EPXAQGB
廠商: Freescale Semiconductor
文件頁數(shù): 50/151頁
文件大?。?/td> 0K
描述: IC MPU PWRQUICC III 783FCPBGA
產(chǎn)品培訓(xùn)模塊: MPC8548 PowerQUICC III Processors
標(biāo)準(zhǔn)包裝: 1
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.0GHz
電壓: 1.1V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
Freescale Semiconductor
143
System Design Information
22.10 Guidelines for High-Speed Interface Termination
This section provides the guidelines for high-speed interface termination when the SerDes interface is
entirely unused and when it is partly unused.
22.10.1 SerDes Interface Entirely Unused
If the high-speed SerDes interface is not used at all, the unused pin must be terminated as described in this
section.
The following pins must be left unconnected (float):
SD_TX[7:0]
Reserved pins T22, T23, M20, M21
The following pins must be connected to GND:
SD_RX[7:0]
SD_REF_CLK
SD_REF_CLK
NOTE
It is recommended to power down the unused lane through SRDSCR1[0:7]
register (offset = 0xE_0F08) (This prevents the oscillations and holds the
receiver output in a fixed state.) that maps to SERDES lane 0 to lane 7
accordingly.
Pins V28 and M26 must be tied to XVDD. Pins V27 and M25 must be tied to GND through a 300-
resistor.
In Rev 2.0 silicon, POR configuration pin cfg_srds_en on TSEC4_TXD[2]/TSEC3_TXD[6] can be used
to power down SerDes block.
22.10.2 SerDes Interface Partly Unused
If only part of the high-speed SerDes interface pins are used, the remaining high-speed serial I/O pins must
be terminated as described in this section.
The following pins must be left unconnected (float) if not used:
SD_TX[7:0]
Reserved pins: T22, T23, M20, M21
The following pins must be connected to GND if not used:
SD_RX[7:0]
SD_REF_CLK
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