參數(shù)資料
型號： MPC8548EPXAQGB
廠商： Freescale Semiconductor
文件頁數(shù)： 63/151頁
文件大?。?/td> 0K
描述： IC MPU PWRQUICC III 783FCPBGA
產(chǎn)品培訓(xùn)模塊： MPC8548 PowerQUICC III Processors
標(biāo)準(zhǔn)包裝： 1
系列： MPC85xx
處理器類型： 32-位 MPC85xx PowerQUICC III
速度： 1.0GHz
電壓： 1.1V
安裝類型： 表面貼裝
封裝/外殼： 783-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 783-FCPBGA（29x29）
包裝： 托盤
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
Freescale Semiconductor
19
RESET Initialization
5
RESET Initialization
This section describes the AC electrical specifications for the RESET initialization timing requirements of
the device. The following table provides the RESET initialization AC timing specifications for the DDR
SDRAM component(s).
The following table provides the PLL lock times.
5.1
Power-On Ramp Rate
This section describes the AC electrical specifications for the power-on ramp rate requirements.
Controlling the maximum power-on ramp rate is required to avoid falsely triggering the ESD circuitry. The
following table provides the power supply ramp rate specifications.
Table 8. RESET Initialization Timing Specifications
Parameter/Condition
Min
Max
Unit
Notes
Required assertion time of HRESET
100
—
s—
Minimum assertion time for SRESET
3
—
SYSCLKs
1
PLL input setup time with stable SYSCLK before HRESET negation
100
—
s—
Input setup time for POR configs (other than PLL config) with respect to
negation of HRESET
4
—
SYSCLKs
1
Input hold time for all POR configs (including PLL config) with respect to
negation of HRESET
2
—
SYSCLKs
1
Maximum valid-to-high impedance time for actively driven POR configs with
respect to negation of HRESET
—
5
SYSCLKs
1
Note:
1. SYSCLK is the primary clock input for the device.
Table 9. PLL Lock Times
Parameter/Condition
Min
Max
Unit
Core and platform PLL lock times
—
100
s
Local bus PLL lock time
—
50
s
PCI/PCI-X bus PLL lock time
—
50
s
Table 10. Power Supply Ramp Rate
Parameter
Min
Max
Unit
Notes
Required ramp rate for MVREF
—
3500
V/s
1
Required ramp rate for VDD
—
4000
V/s
1, 2
Note:
1. Maximum ramp rate from 200 to 500 mV is most critical as this range may falsely trigger the ESD circuitry.
2. VDD itself is not vulnerable to false ESD triggering; however, as per Section 22.2, “PLL Power Supply Filtering,” the
recommended AVDD_CORE, AVDD_PLAT, AVDD_LBIU, AVDD_PCI1 and AVDD_PCI2 filters are all connected to VDD.
Their ramp rates must be equal to or less than the VDD ramp rate.
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參數(shù)描述
MPC8548EPXAQGD 功能描述:微處理器 - MPU PQ38 PB ST WE 1000 R3.0 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8548EPXATGA 制造商:Freescale Semiconductor 功能描述:MPC85XX RISC 32-BIT CMOS 1.2GHZ 1.8V/2.5V/3.3V 783-PIN BGA T - Bulk
MPC8548EPXATGB 功能描述:微處理器 - MPU FG PQ38 8548 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8548EPXAUJA 制造商:Freescale Semiconductor 功能描述:MPC85XX RISC 32-BIT CMOS 1.333GHZ 1.8V/2.5V/3.3V 783-PIN BGA - Bulk
MPC8548EPXAUJB 功能描述:微處理器 - MPU FG PQ38 8548 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
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