參數(shù)資料
型號(hào): MPC8555ECPXALE
廠商: FREESCALE SEMICONDUCTOR INC
元件分類(lèi): 微控制器/微處理器
英文描述: RISC PROCESSOR, PBGA783
封裝: 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, FLIP CHIP, PLASTIC, BGA-783
文件頁(yè)數(shù): 28/88頁(yè)
文件大?。?/td> 1110K
代理商: MPC8555ECPXALE
MPC8555E PowerQUICC III Integrated Communications Processor Hardware Specification, Rev. 4.2
34
Freescale Semiconductor
Local Bus
9.2
Local Bus AC Electrical Specifications
Table 30 describes the general timing parameters of the local bus interface of the MPC8555E with the DLL
enabled.
Table 30. Local Bus General Timing Parameters—DLL Enabled
Parameter
Configuration 7
Symbol 1
Min
Max
Unit
Notes
Local bus cycle time
tLBK
6.0
ns
2
LCLK[n] skew to LCLK[m] or LSYNC_OUT
tLBKSKEW
150
ps
7, 9
Input setup to local bus clock (except
LUPWAIT)
tLBIVKH1
1.8
ns
3, 4, 8
LUPWAIT input setup to local bus clock
tLBIVKH2
1.7
ns
3, 4
Input hold from local bus clock (except
LUPWAIT)
tLBIXKH1
0.5
ns
3, 4, 8
LUPWAIT input hold from local bus clock
tLBIXKH2
1.0
ns
3, 4
LALE output transition to LAD/LDP output
transition (LATCH hold time)
tLBOTOT
1.5
ns
6
Local bus clock to output valid (except
LAD/LDP and LALE)
LWE[0:1] = 00
tLBKHOV1
2.3
ns
3, 8
LWE[0:1] = 11 (default)
3.8
Local bus clock to data valid for LAD/LDP
LWE[0:1] = 00
tLBKHOV2
2.5
ns
3, 8
LWE[0:1] = 11 (default)
4.0
Local bus clock to address valid for LAD
LWE[0:1] = 00
tLBKHOV3
2.6
ns
3, 8
LWE[0:1] = 11 (default)
4.1
Output hold from local bus clock (except
LAD/LDP and LALE)
LWE[0:1] = 00
tLBKHOX1
0.7
ns
3, 8
LWE[0:1] = 11 (default)
1.6
Output hold from local bus clock for
LAD/LDP
LWE[0:1] = 00
tLBKHOX2
0.7
ns
3, 8
LWE[0:1] = 11 (default)
1.6
Local bus clock to output high Impedance
(except LAD/LDP and LALE)
LWE[0:1] = 00
tLBKHOZ1
2.8
ns
5, 9
LWE[0:1] = 11 (default)
4.2
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