參數(shù)資料
型號: MPC8555VTALD
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 667 MHz, RISC PROCESSOR, PBGA783
封裝: 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, LEAD FREE, FLIP CHIP, PLASTIC, BGA-783
文件頁數(shù): 41/88頁
文件大?。?/td> 772K
代理商: MPC8555VTALD
MPC8555E PowerQUICC III Integrated Communications Processor Hardware Specification, Rev. 3.1
46
Freescale Semiconductor
CPM
Figure 28 shows TDM input and output signals.
Figure 28. TDM Signal AC Timing Diagram
1 SPI AC timings are internal mode when it is master since SPICLK is an
output, and external mode when it is slave.
2 SPI AC timings refer always to SPICLK.
Figure 29. PIO Signal Diagram
10.3
CPM I2C AC Specification
Table 35. I2C Timing
Characteristic
Expression
All Frequencies
Unit
Min
Max
SCL clock frequency (slave)
fSCL
0FMAX
1
Hz
SCL clock frequency (master)
fSCL
BRGCLK/16512
BRGCLK/48
Hz
Bus free time between transmissions
tSDHDL
1/(2.2 * fSCL)-
s
Low period of SCL
tSCLCH
1/(2.2 * fSCL)-
s
High period of SCL
tSCHCL
1/(2.2 * fSCL)-
s
Start condition setup time2
tSCHDL
2/(divider * fSCL)
- 2
s
Start condition hold time2
tSDLCL
3/(divider * fSCL)-
s
Serial CLKIN
tTDKHOX
TDM Input Signals
There are 4 possible TDM timing conditions:
tTDIVKH
tTDIXKH
TDM Output Signals
Note:
1.
2.
3.
4.
Input sampled on the rising edge and output driven on the rising edge (shown).
Input sampled on the rising edge and output driven on the falling edge.
Input sampled on the falling edge and output driven on the falling edge.
Input sampled on the falling edge and output driven on the rising edge.
Sys clk
PIO inputs
PIO outputs
tPIIVKH
tPIIXKH
tPIKHOX
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