參數(shù)資料
型號(hào): MPC8555VTAQEX
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 1000 MHz, RISC PROCESSOR, PBGA783
封裝: 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, LEAD FREE, FLIP CHIP, PLASTIC, BGA-783
文件頁數(shù): 42/88頁
文件大小: 1244K
代理商: MPC8555VTAQEX
MPC8555E PowerQUICC III Integrated Communications Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
47
CPM
Figure 29. PIO Signal Diagram
10.3
CPM I2C AC Specification
Table 35. I2C Timing
Characteristic
Expression
All Frequencies
Unit
Min
Max
SCL clock frequency (slave)
fSCL
0FMAX
(1)
Notes:
1.
FMAX = BRGCLK/(min_divider*prescale. Where prescaler=25-I2MODE[PDIV]; and min_divider=12 if digital filter disabled
and 18 if enabled.
Example #1: if I2MODE[PDIV]=11 (prescaler=4) and I2MODE[FLT]=0 (digital filter disabled) then FMAX=BRGCLK/48
Example #2: if I2MODE[PDIV]=00 (prescaler=32) and I2MODE[FLT]=1 (digital filter enabled) then FMAX=BRGCLK/576
Hz
SCL clock frequency (master)
fSCL
BRGCLK/16512
BRGCLK/48
Hz
Bus free time between transmissions
tSDHDL
1/(2.2 * fSCL)-
s
Low period of SCL
tSCLCH
1/(2.2 * fSCL)-
s
High period of SCL
tSCHCL
1/(2.2 * fSCL)-
s
Start condition setup time2
tSCHDL
2/(divider * fSCL)
- (2)
2. divider = fSCL/prescaler.
In master mode: divider=BRGCLK/(fSCL*prescaler)=2*(I2BRG[DIV]+3)
In slave mode: divider=BRGCLK/(fSCL*prescaler)
s
Start condition hold time2
tSDLCL
3/(divider * fSCL)-
s
Data hold time 2
tSCLDX
2/(divider * fSCL)-
s
Data setup time2
tSDVCH
3/(divider * fSCL)-
s
SDA/SCL rise time
tSRISE
-
1/(10 * fSCL)s
SDA/SCL fall time
tSFALL
-
1/(33 * fSCL)s
Stop condition setup time
tSCHDH
2/(divider * fSCL)
-
s
Sys clk
PIO inputs
PIO outputs
tPIIVKH
tPIIXKH
tPIKHOX
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