參數(shù)資料
型號(hào): MPC8560PXALDB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 667 MHz, RISC PROCESSOR, PBGA783
封裝: 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, FLIP CHIP, PLASTIC, BGA-783
文件頁(yè)數(shù): 18/108頁(yè)
文件大?。?/td> 2170K
代理商: MPC8560PXALDB
MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1
Freescale Semiconductor
17
Clock Timing
4
Clock Timing
4.1 System Clock Timing
Table 7 provides the system clock (SYSCLK) AC timing specifications for the MPC8560.
4.2 TSEC Gigabit Reference Clock Timing
Table 7 provides the TSEC gigabit reference clock (EC_GTX_CLK125) AC timing specifications for the MPC8560.
Table 7. SYSCLK AC Timing Specifications
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Notes
SYSCLK frequency
fSYSCLK
166
MHz
1
SYSCLK cycle time
tSYSCLK
6.0
ns
SYSCLK rise and fall time
tKH, tKL
0.6
1.0
1.2
ns
2
SYSCLK duty cycle
tKHKL/tSYSCLK
40
60
%
3
SYSCLK jitter
+/- 150
ps
4, 5
Notes:
1.Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting
SYSCLK frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or
PLL Ratio,” for ratio settings.
2. Rise and fall times for SYSCLK are measured at 0.4 V and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at -20 dB. The bandwidth must be set low to
allow cascade-connected PLL-based devices to track SYSCLK drivers with the specified jitter.
Table 8. EC_GTX_CLK125 AC Timing Specifications
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Notes
EC_GTX_CLK125 frequency
fG125
125
MHz
EC_GTX_CLK125 cycle time
tG125
8
ns
EC_GTX_CLK125 duty cycle
GMII, TBI
RGMII, RTBI
tG125H/tG125
45
47
55
53
%
1
Notes:
1. Timing is guaranteed by design and characterization.
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