參數(shù)資料
型號(hào)： MPC8560PXALDB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 667 MHz, RISC PROCESSOR, PBGA783
封裝： 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, FLIP CHIP, PLASTIC, BGA-783
文件頁數(shù)： 22/108頁
文件大?。?/td> 2170K
代理商： MPC8560PXALDB
MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1
20
Freescale Semiconductor
DDR SDRAM
6
DDR SDRAM
This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the MPC8560.
6.1 DDR SDRAM DC Electrical Characteristics
Table 12 provides the recommended operating conditions for the DDR SDRAM component(s) of the MPC8560.
Table 13 provides the DDR capacitance.
Table 12. DDR SDRAM DC Electrical Characteristics
Parameter/Condition
Symbol
Min
Max
Unit
Notes
I/O supply voltage
GVDD
2.375
2.625
V
1
I/O reference voltage
MVREF
0.49
× GVDD
0.51
× GVDD
V
2
I/O termination voltage
VTT
MVREF – 0.04
MVREF + 0.04
V
3
Input high voltage
VIH
MVREF + 0.18
GVDD + 0.3
V
4
Input low voltage
VIL
–0.3
MVREF – 0.18
V
4
Output leakage current
IOZ
–10
10
A
5
Output high current (VOUT = 1.95 V)
IOH
–15.2
—
mA
Output low current (VOUT = 0.35 V)
IOL
15.2
—
mA
MVREF input leakage current
IVREF
—
5
A
Notes:
1.GVDD is expected to be within 50 mV of the DRAM GVDD at all times.
2.MVREF is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver.
Peak-to-peak noise on MVREF may not exceed ±2% of the DC value.
3.VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected
to be equal to MVREF. This rail should track variations in the DC level of MVREF.
4.VIH can tolerate an overshoot of 1.2V over GVDD for a pulse width of ≤3 ns, and the pulse width cannot be greater
than tMCK. VIL can tolerate an undershoot of 1.2V below GND for a pulse width of ≤3 ns, and the pulse width cannot
be greater than tMCK.
5.Output leakage is measured with all outputs disabled, 0 V
≤ V
OUT ≤ GVDD.
Table 13. DDR SDRAM Capacitance
Parameter/Condition
Symbol
Min
Max
Unit
Notes
Input/output capacitance: DQ, DQS, MSYNC_IN
CIO
6
8
pF
1
Delta input/output capacitance: DQ, DQS
CDIO
—
0.5
pF
1
Note:
1.This parameter is sampled. GVDD = 2.5 V ± 0.125 V, f = 1 MHz, TA = 25°C, VOUT = GVDD/2, VOUT (peak to peak) =
0.2 V.
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