參數(shù)資料
型號(hào): MPC8560VTAQJC
廠商: FREESCALE SEMICONDUCTOR INC
元件分類(lèi): 微控制器/微處理器
英文描述: 32-BIT, 1000 MHz, RISC PROCESSOR, PBGA783
封裝: 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, LEAD FREE, FLIP CHIP, PLASTIC, BGA-783
文件頁(yè)數(shù): 18/108頁(yè)
文件大?。?/td> 1379K
代理商: MPC8560VTAQJC
MPC8560 Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
17
DDR SDRAM
Table 12 provides the PLL and DLL lock times.
6 DDR SDRAM
This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the
MPC8560.
6.1 DDR SDRAM DC Electrical Characteristics
Table 13 provides the recommended operating conditions for the DDR SDRAM component(s) of the
MPC8560.
Maximum valid-to-high impedance time for actively
driven POR configs with respect to negation of HRESET
5
SYSCLKs
1
Notes:
1.SYSCLK is identical to the PCI_CLK signal and is the primary clock input for the MPC8560. See the MPC8560
PowerQUICC III Integrated Communications Processor Preliminary Reference Manual for more details.
Table 12. PLL and DLL Lock Times
Parameter/Condition
Min
Max
Unit
Notes
PLL lock times
100
μs
DLL lock times
7680
122,880
CCB Clocks
1, 2
Notes:
1.DLL lock times are a function of the ratio between the output clock and the platform (or CCB) clock. A 2:1 ratio
results in the minimum and an 8:1 ratio results in the maximum.
2. The CCB clock is determined by the SYSCLK
× platform PLL ratio.
Table 13. DDR SDRAM DC Electrical Characteristics
Parameter/Condition
Symbol
Min
Max
Unit
Notes
I/O supply voltage
GVDD
2.375
2.625
V
1
I/O reference voltage
MVREF
0.49
× GV
DD
0.51
× GV
DD
V2
I/O termination voltage
VTT
MVREF – 0.04
MVREF + 0.04
V
3
Input high voltage
VIH
MVREF + 0.18
GVDD + 0.3
V
4
Input low voltage
VIL
–0.3
MVREF – 0.18
V
4
Output leakage current
IOZ
–10
10
μA5
Output high current (VOUT = 1.95 V)
IOH
–15.2
mA
Output low current (VOUT = 0.35 V)
IOL
15.2
mA
Table 11. RESET Initialization Timing Specifications (continued)
Parameter/Condition
Min
Max
Unit
Notes
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