參數(shù)資料
型號: MPC8568ECVTANGGA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 800 MHz, RISC PROCESSOR, PBGA1023
封裝: 33 X 33 MM, 2.75 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, FCBGA-1023
文件頁數(shù): 4/139頁
文件大?。?/td> 1449K
代理商: MPC8568ECVTANGGA
MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
101
Package and Pinout
4.
Maximum solder ball diameter measured parallel to datum A.
5.
Datum A, the seating plane, is defined by the spherical crowns of the solder balls.
6.
ParalleUsm measurement shall exclude any effect of mark on top surface of package
7.
Capacitors may not be present on all devices.
8.
Caution must be taken not to short capacitors or exposed metal capacitor pads on top of package.
22.3
Pinout Listings
Some of the non-QE signals are multiplexed with QE port pins, as follows:
PC[0]
UART_SOUT[1]
PC[1]
UART_RTS[1]
PC[2]
UART_CTS[1]
PC[3]
UART_SIN[1]
PC[11]
IRQ[8]
PC[12]
IRQ[9]/DMA_DREQ[3]
PC[13]
IRQ[10]/DMA_DACK[3]
PC[14]
IRQ[11]/DMA_DDONE[3]
PC[15]
DMA_DREQ[1]
PC[16]
DMA_DACK[1]
PC[17]
DMA_DDONE[1]
PC[18]
IIC2_SCL
PC[19]
IIC2_SDA
PD[28]
UART_SOUT[1]
PD[29]
UART_RTS[1]
PD[30]
UART_CTS[1]
PD[31]
UART_SIN[1]
This applies to both MPC8568E and MPC8568E. Note that for DUART1, there are two options. DUART0
is multiplexed with PCI Req/Grant pins.
PCI_REQ[3]
UART_CTS[0]
PCI_REQ[4]
UART_SIN[0]
PCI_GNT[3]
UART_RTS[0]
PCI_GNT[4]
UART_SOUT[0]
For MPC8568E, GPIO is multiplexed with the TSEC2 interface:
TSEC2_TXD[7:0]
GPOUT[0:7]
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