參數(shù)資料
型號: MPC8569EVTAQLJB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: RISC PROCESSOR, PBGA783
封裝: 29 X 29 MM, 1 MM PITCH, PLASTIC, BGA-783
文件頁數(shù): 87/126頁
文件大?。?/td> 2847K
代理商: MPC8569EVTAQLJB
Ethernet Interface
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
Freescale Semiconductor
63
2.6.3.6
TBI Single-Clock Mode AC Specifications
The following table shows the TBI single-clock mode receive AC timing specifications.
The following figure shows the TBI single-clock mode receive AC timing diagram.
Figure 25. TBI Single-Clock Mode Receive AC Timing Diagram
2.6.3.7
RGMII and RTBI AC Timing Specifications
The following table presents the RGMII and RTBI AC timing specifications.
Table 34. TBI Single-Clock Mode Receive AC Timing Specifications
For recommended operating conditions, see Table 3
Parameter
Symbol
Min
Typ
Max
Unit
Note
RX_CLK clock period
tTRR
7.5
8.0
8.5
ns
1
RX_CLK duty cycle
tTRRH
40
50
60
%
2
RX_CLK peak-to-peak jitter
tTRRJ
——
250
ps
2
Rise time RX_CLK (20%–80%)
tTRRR
———
ns
2
Fall time RX_CLK (80%–20%)
tTRRF
———
ns
2
RCG[9:0] setup time to RX_CLK rising edge
tTRRDV
2.0
ns
RCG[9:0] hold time to RX_CLK rising edge
tTRRDX
1.0
ns
Note:
1. The frequency of RX_CLK should not exceed the frequency of gigabit Ethernet reference clock by more than 300 ppm.
2. System/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is
guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.
Table 35. RGMII and RTBI AC Timing Specifications
For recommended operating conditions, see Table 3
Parameter
Symbol1
Min
Typ
Max
Unit
Notes
Data to clock output skew (at transmitter)
tSKRGT_TX
–500
0
500
ps
5
Data to clock input skew (at receiver)
tSKRGT_RX
1.2
2.6
ns
2
Clock period duration
tRGT
7.2
8.0
8.8
ns
3
Duty cycle for 10BASE-T and 100BASE-TX
tRGTH/tRGT
40
50
60
%
3, 4, 6
tTRR
tTRRH
tTRRF
tTRRR
RX_CLK
RCG[9:0]
Valid Data
tTRRDX
tTRRDV
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