參數(shù)資料
型號(hào): MPC859T
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Hardware Specifications
中文描述: 硬件規(guī)格
文件頁數(shù): 49/92頁
文件大小: 1274K
代理商: MPC859T
MOTOROLA
MPC866/859 Hardware Specifications
For More Information On This Product,
Go to: www.freescale.com
49
CPM Electrical Characteristics
Figure 46 shows the port C interrupt detection timing.
Figure 46. Port C Interrupt Detection Timing
12.3
IDMA Controller AC Electrical Specifications
Table 18 shows the IDMA controller timings as shown in Figure 47 through Figure 50.
Figure 47. IDMA External Requests Timing Diagram
Table 18. IDMA Controller Timing
Num
Characteristic
All Frequencies
Unit
Min
Max
40
DREQ setup time to clock high
7
ns
41
DREQ hold time from clock high
3
ns
42
SDACK assertion delay from clock high
12
ns
43
SDACK negation delay from clock low
12
ns
44
SDACK negation delay from TA low
20
ns
45
SDACK negation delay from clock high
15
ns
46
TA assertion to falling edge of the clock setup time (applies to external TA)
7
ns
Port C
(Input)
35
36
41
40
DREQ
(Input)
CLKO
(Output)
F
Freescale Semiconductor, Inc.
n
.
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