參數(shù)資料
型號(hào): MPC885
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: Hardware Specifications
中文描述: 硬件規(guī)格
文件頁(yè)數(shù): 16/92頁(yè)
文件大小: 1499K
代理商: MPC885
MPC885/MPC880 Hardware Specifications, Rev. 3
16
Freescale Semiconductor
Bus Signal Timing
Table 9
provides the timings for the MPC885/880 at 33-, 40-, 66-, and 80-MHz bus operation.
The timing for the MPC885/880 bus shown assumes a 50-pF load for maximum delays and a 0-pF load for minimum
delays. CLKOUT assumes a 100-pF load maximum delay.
Table 9. Bus Operation Timings
Table 7. Frequency Ranges for Standard Part Frequencies (1:1 Bus Mode)
Part Frequency
66 MHz
80 MHz
Min
Max
Min
Max
Core frequency
40
66.67
40
80
Bus frequency
40
66.67
40
80
Table 8. Frequency Ranges for Standard Part Frequencies (2:1 Bus Mode)
Part Frequency
66 MHz
80 MHz
133 MHz
Min
Max
Min
Max
Min
Max
Core frequency
40
66.67
40
80
40
133
Bus frequency
20
33.33
20
40
20
66
Num
Characteristic
33 MHz
40 MHz
66 MHz
80 MHz
Unit
Min
Max
Min
Max
Min
Max
Min
Max
B1
Bus period (CLKOUT), see
Table 7
ns
B1a
EXTCLK to CLKOUT phase skew - If
CLKOUT is an integer multiple of
EXTCLK, then the rising edge of EXTCLK
is aligned with the rising edge of CLKOUT.
For a non-integer multiple of EXTCLK, this
synchronization is lost, and the rising
edges of EXTCLK and CLKOUT have a
continuously varying phase skew.
–2
+2
–2
+2
–2
+2
–2
+2
ns
B1b
CLKOUT frequency jitter peak-to-peak
1
1
1
1
ns
B1c
Frequency jitter on EXTCLK
0.50
0.50
0.50
0.50
%
B1d
CLKOUT phase jitter peak-to-peak
for OSCLK
15 MHz
4
4
4
4
ns
CLKOUT phase jitter peak-to-peak
for OSCLK < 15 MHz
5
5
5
5
ns
B2
CLKOUT pulse width low
(MIN = 0.4
×
B1, MAX = 0.6
×
B1)
12.1
18.2
10.0
15.0
6.1
9.1
5.0
7.5
ns
B3
CLKOUT pulse width high
(MIN = 0.4
×
B1, MAX = 0.6
×
B1)
12.1
18.2
10.0
15.0
6.1
9.1
5.0
7.5
ns
B4
CLKOUT rise time
4.00
4.00
4.00
4.00
ns
B5
CLKOUT fall time
4.00
4.00
4.00
4.00
ns
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