參數(shù)資料
型號(hào): MPC885ZP66
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 60/87頁(yè)
文件大?。?/td> 0K
描述: IC MPU POWERQUICC 66MHZ 357PBGA
標(biāo)準(zhǔn)包裝: 44
系列: MPC8xx
處理器類(lèi)型: 32-位 MPC8xx PowerQUICC
速度: 66MHz
電壓: 3.3V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 357-BBGA
供應(yīng)商設(shè)備封裝: 357-PBGA(25x25)
包裝: 托盤(pán)
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
63
CPM Electrical Characteristics
Figure 64. Ethernet Transmit Timing Diagram
12.9
SMC Transparent AC Electrical Specifications
Table 25 provides the SMC transparent timings as shown in Figure 65.
Table 25. SMC Transparent Timing
Num
Characteristic
All Frequencies
Unit
Min
Max
150
SMCLK clock period1
1
SyncCLK must be at least twice as fast as SMCLK.
100
ns
151
SMCLK width low
50
ns
151A
SMCLK width high
50
ns
152
SMCLK rise/fall time
15
ns
153
SMTXD active delay (from SMCLK falling edge)
10
50
ns
154
SMRXD/SMSYNC setup time
20
ns
155
RXD1/SMSYNC hold time
5
ns
TCLK1
128
TxD1
(Output)
128
TENA(RTS1)
(Input)
Notes:
Transmit clock invert (TCI) bit in GSMR is set.
If RENA is negated before TENA or RENA is not asserted at all during transmit, then the
CSL bit is set in the buffer descriptor at the end of the frame transmission.
1.
2.
RENA(CD1)
(Input)
133
134
132
131
121
129
(Note 2)
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