參數(shù)資料
型號(hào)： MPC885ZP66
廠商： Freescale Semiconductor
文件頁數(shù)： 87/87頁
文件大?。?/td> 0K
描述： IC MPU POWERQUICC 66MHZ 357PBGA
標(biāo)準(zhǔn)包裝： 44
系列： MPC8xx
處理器類型： 32-位 MPC8xx PowerQUICC
速度： 66MHz
電壓： 3.3V
安裝類型： 表面貼裝
封裝/外殼： 357-BBGA
供應(yīng)商設(shè)備封裝： 357-PBGA（25x25）
包裝： 托盤
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
9
Maximum Tolerated Ratings
3
Maximum Tolerated Ratings
This section provides the maximum tolerated voltage and temperature ranges for the MPC885/MPC880.
Table 2 displays the maximum tolerated ratings, and Table 3 displays the operating temperatures.
Figure 3 shows the undershoot and overshoot voltages at the interfaces of the MPC885/MPC880.
Figure 3. Undershoot/Overshoot Voltage for VDDH and VDDL
Table 2. Maximum Tolerated Ratings
Rating
Symbol
Value
Unit
Supply voltage1
1 The power supply of the device must start its ramp from 0.0 V.
VDDH
–0.3 to 4.0
V
VDDL
–0.3 to 2.0
V
VDDSYN
–0.3 to 2.0
V
Difference between VDDL and VDDSYN
<100
mV
Input voltage2
2 Functional operating conditions are provided with the DC electrical specifications in Table 6. Absolute maximum ratings are
stress ratings only; functional operation at the maxima is not guaranteed. Stress beyond those listed may affect device
reliability or cause permanent damage to the device. See Section 8, “Power Supply and Power Sequencing.”
Caution: All inputs that tolerate 5 V cannot be more than 2.5 V greater than VDDH. This restriction applies to power up and
normal operation (that is, if the MPC885/MPC880 is unpowered, a voltage greater than 2.5 V must not be applied to its inputs).
Vin
GND – 0.3 to VDDH
V
Storage temperature range
Tstg
–55 to +150
°C
GND
GND – 0.3 V
GND – 0.7 V
Not to Exceed 10%
VDDH/VDDL + 20%
VDDH/VDDL
VDDH/VDDL + 5%
of tinterface
1
1. tinterface refers to the clock period associated with the bus clock interface.
VIH
VIL
Note:
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