Table 29 provides " />
參數(shù)資料
型號(hào): MPC885ZP66
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 65/87頁(yè)
文件大?。?/td> 0K
描述: IC MPU POWERQUICC 66MHZ 357PBGA
標(biāo)準(zhǔn)包裝: 44
系列: MPC8xx
處理器類型: 32-位 MPC8xx PowerQUICC
速度: 66MHz
電壓: 3.3V
安裝類型: 表面貼裝
封裝/外殼: 357-BBGA
供應(yīng)商設(shè)備封裝: 357-PBGA(25x25)
包裝: 托盤
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
68
Freescale Semiconductor
CPM Electrical Characteristics
Table 29 provides the I2C (SCL > 100 kHz) timings.
Figure 70 shows the I2C bus timing.
Figure 70. I2C Bus Timing Diagram
210
SDL/SCL fall time
300
ns
211
Stop condition setup time
4.7
μs
1 SCL frequency is given by SCL = BRGCLK_frequency/((BRG register + 3) × pre_scaler × 2).
The ratio SyncClk/(BRGCLK/pre_scaler) must be greater or equal to 4/1.
Table 29. I2C Timing (SCL > 100 kHZ)
Num
Characteristic
Expression
All Frequencies
Unit
Min
Max
200
SCL clock frequency (slave)
fSCL
0
BRGCLK/48
Hz
200
SCL clock frequency (master)1
1 SCL frequency is given by SCL = BrgClk_frequency/((BRG register + 3) × pre_scaler × 2).
The ratio SyncClk/(Brg_Clk/pre_scaler) must be greater or equal to 4/1.
fSCL
BRGCLK/16512
BRGCLK/48
Hz
202
Bus free time between transmissions
1/(2.2
× fSCL)
s
203
Low period of SCL
1/(2.2
× fSCL)
s
204
High period of SCL
1/(2.2
× fSCL)
s
205
Start condition setup time
1/(2.2
× fSCL)
s
206
Start condition hold time
1/(2.2
× fSCL)
s
207
Data hold time
0
s
208
Data setup time
1/(40
× fSCL)
s
209
SDL/SCL rise time
1/(10
× fSCL)
s
210
SDL/SCL fall time
1/(33
× fSCL)
s
211
Stop condition setup time
1/2(2.2
× fSCL)
s
Table 28. I2C Timing (SCL < 100 kHZ) (continued)
Num
Characteristic
All Frequencies
Unit
Min
Max
SCL
202
205
203
207
204
208
206
209
211
210
SDA
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