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參數(shù)資料
| 型號： | MPC885ZP80 |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; Body Material:Aluminum; Series:PT07; Number of Contacts:12; Connector Shell Size:14; Connecting Termination:Solder; Circular Shell Style:Jam Nut Receptacle; Circular Contact Gender:Socket |
| 中文描述： | 硬件規(guī)格 |
| 文件頁數(shù)： | 3/92頁 |
| 文件大小： | 1499K |
| 代理商： | MPC885ZP80 |
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MPC885/MPC880 Hardware Specifications, Rev. 3
Freescale Semiconductor
3
Features
— UTOPIA L2-compliant interface with added FIFO buffering to reduce the total cell
transmission time and multi-PHY support. (The earlier UTOPIA L1 specification is also
supported.)
— Parameter RAM for both SPI and I
2
C can be relocated without RAM-based microcode
— Supports full-duplex UTOPIA master (ATM side) and slave (PHY side) operations using a split
bus
— AAL2/VBR functionality is ROM-resident.
Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
32 address lines
Memory controller (eight banks)
— Contains complete dynamic RAM (DRAM) controller
— Each bank can be a chip select or RAS to support a DRAM bank.
— Up to 30 wait states programmable per memory bank
— Glueless interface to DRAM, SIMMS, SRAM, EPROMs, Flash EPROMs, and other memory
devices
— DRAM controller programmable to support most size and speed memory interfaces
— Four CAS lines, four WE lines, and one OE line
— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
— Variable block sizes (32 Kbyte–256 Mbyte)
— Selectable write protection
— On-chip bus arbitration logic
General-purpose timers
— Four 16-bit timers or two 32-bit timers
— Gate mode can enable/disable counting.
— Interrupt can be masked on reference match and event capture
Two fast Ethernet controllers (FEC)—Two 10/100 Mbps Ethernet/IEEE 802.3 CDMA/CS that
interface through MII and/or RMII interfaces
System integration unit (SIU)
— Bus monitor
— Software watchdog
— Periodic interrupt timer (PIT)
— Clock synthesizer
— Decrementer and time base
— Reset controller
— IEEE 1149.1 test access port (JTAG)
Security engine is optimized to handle all the algorithms associated with IPsec, SSL/TLS, SRTP,
802.11i, and iSCSI processing. Available on the MPC885, the security engine contains a
crypto-channel, a controller, and a set of crypto hardware accelerators (CHAs). The CHAs are:
— Data encryption standard execution unit (DEU)
– DES, 3DES
– Two key (K1, K2, K1) or three key (K1, K2, K3)
– ECB and CBC modes for both DES and 3DES
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| MPC885ZP66 | Circular Connector; Body Material:Aluminum; Series:PT07; No. of Contacts:41; Connector Shell Size:22; Connecting Termination:Solder; Circular Shell Style:Jam Nut Receptacle; Circular Contact Gender:Pin; Insert Arrangement:22-41 |
| MPC885CZP66 | PT 55C 55#20 PIN RECP |
| MPC885ZP133 | Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT07; No. of Contacts:4; Connector Shell Size:8; Connecting Termination:Solder; Circular Shell Style:Jam Nut Receptacle; Body Style:Straight |
| MPC885CZP133 | Hardware Specifications |
| MPC92433 | 1428 MHz Dual Output LVPECL Clock Synthesizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC-8890 | 制造商:AAEON 制造商全稱:AAEON 功能描述:Intel Pentium M or Celeron M Processors |
| MPC-8890-A10 | 制造商:AAEON 制造商全稱:AAEON 功能描述:Intel Pentium M or Celeron M Processors |
| MPC-8890-A10-01 | 制造商:AAEON 制造商全稱:AAEON 功能描述:Intel Pentium M or Celeron M Processors |
| MPC-8890-A10-02 | 制造商:AAEON 制造商全稱:AAEON 功能描述:Intel Pentium M or Celeron M Processors |
| MPC-8890-A10-03 | 制造商:AAEON 制造商全稱:AAEON 功能描述:Intel Pentium M or Celeron M Processors |
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